[{"date_updated":"2022-04-18T10:04:21Z","_id":"30907","page":"1-1","status":"public","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"type":"journal_article","year":"2021","language":[{"iso":"eng"}],"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","publication":"IEEE Transactions on Computers","date_created":"2022-04-18T10:03:16Z","department":[{"_id":"78"}],"user_id":"398","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"publication_status":"published","citation":{"chicago":"Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, 2021, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>.","ieee":"A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","apa":"Rodriguez, A., Otero, A., Platzner, M., &#38; De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>","ama":"Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>. Published online 2021:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>","short":"A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1.","mla":"Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","bibtex":"@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }"},"doi":"10.1109/tc.2021.3107196","author":[{"first_name":"Alfonso","full_name":"Rodriguez, Alfonso","last_name":"Rodriguez"},{"last_name":"Otero","full_name":"Otero, Andres","first_name":"Andres"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"De la Torre","full_name":"De la Torre, Eduardo","first_name":"Eduardo"}],"title":"Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs"}]