---
_id: '16416'
abstract:
- lang: eng
  text: The advent of FPGA-based hybrid architecture offers the opportunity of customizing
    memory subsystems to enhance the overall system performance. However, it is not
    straightforward to design efficient FPGA circuits for emerging FPGAs applications
    such as in-memory database and graph analytics, which heavily depend on concurrent
    data structures (CDS'). Highly dynamic behaviors of CDS' have to be orchestrated
    by synchronization primitives for correct execution. These primitives induce overwhelming
    memory traffic for synchronizations on FPGAs. This paper proposes a novel method
    for systematically exploring and exploiting memory-level parallelism (MLP) of
    CDS by transactional execution on FPGAs. Inspired by the idea that semantics of
    transactions can be implemented in a more efficient and scalable manner on FPGAs
    than on CPUs, we propose a transaction-based reconfigurable runtime system for
    capturing MLP of CDS'. Experiments on linked-list and skip-list show our approach
    achieves 5.18x and 1.55x throughput improvement on average than lock-based FPGA
    implementations and optimized CDS algorithms on a state-of-the-art multi-core
    CPU respectively.
author:
- first_name: Zhaoshi
  full_name: Li, Zhaoshi
  last_name: Li
- first_name: Leibo
  full_name: Liu, Leibo
  last_name: Liu
- first_name: Yangdong
  full_name: Deng, Yangdong
  last_name: Deng
- first_name: Shouyi
  full_name: Yin, Shouyi
  last_name: Yin
- first_name: Shaojun
  full_name: Wei, Shaojun
  last_name: Wei
citation:
  ama: Li Z, Liu L, Deng Y, Yin S, Wei S. Breaking the Synchronization Bottleneck
    with Reconfigurable Transactional Execution. <i>IEEE Computer Architecture Letters</i>.
    2018:147-150. doi:<a href="https://doi.org/10.1109/lca.2018.2828402">10.1109/lca.2018.2828402</a>
  apa: Li, Z., Liu, L., Deng, Y., Yin, S., &#38; Wei, S. (2018). Breaking the Synchronization
    Bottleneck with Reconfigurable Transactional Execution. <i>IEEE Computer Architecture
    Letters</i>, 147–150. <a href="https://doi.org/10.1109/lca.2018.2828402">https://doi.org/10.1109/lca.2018.2828402</a>
  bibtex: '@article{Li_Liu_Deng_Yin_Wei_2018, title={Breaking the Synchronization
    Bottleneck with Reconfigurable Transactional Execution}, DOI={<a href="https://doi.org/10.1109/lca.2018.2828402">10.1109/lca.2018.2828402</a>},
    journal={IEEE Computer Architecture Letters}, author={Li, Zhaoshi and Liu, Leibo
    and Deng, Yangdong and Yin, Shouyi and Wei, Shaojun}, year={2018}, pages={147–150}
    }'
  chicago: Li, Zhaoshi, Leibo Liu, Yangdong Deng, Shouyi Yin, and Shaojun Wei. “Breaking
    the Synchronization Bottleneck with Reconfigurable Transactional Execution.” <i>IEEE
    Computer Architecture Letters</i>, 2018, 147–50. <a href="https://doi.org/10.1109/lca.2018.2828402">https://doi.org/10.1109/lca.2018.2828402</a>.
  ieee: Z. Li, L. Liu, Y. Deng, S. Yin, and S. Wei, “Breaking the Synchronization
    Bottleneck with Reconfigurable Transactional Execution,” <i>IEEE Computer Architecture
    Letters</i>, pp. 147–150, 2018.
  mla: Li, Zhaoshi, et al. “Breaking the Synchronization Bottleneck with Reconfigurable
    Transactional Execution.” <i>IEEE Computer Architecture Letters</i>, 2018, pp.
    147–50, doi:<a href="https://doi.org/10.1109/lca.2018.2828402">10.1109/lca.2018.2828402</a>.
  short: Z. Li, L. Liu, Y. Deng, S. Yin, S. Wei, IEEE Computer Architecture Letters
    (2018) 147–150.
date_created: 2020-04-06T11:49:12Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/lca.2018.2828402
keyword:
- pc2-harp-ressources
language:
- iso: eng
page: 147-150
publication: IEEE Computer Architecture Letters
publication_identifier:
  issn:
  - 1556-6056
  - 1556-6064
  - 2473-2575
publication_status: published
status: public
title: Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution
type: journal_article
user_id: '61189'
year: '2018'
...