[{"date_updated":"2025-11-14T09:35:16Z","publisher":"MECOnet","date_created":"2025-11-14T05:48:05Z","author":[{"first_name":"Atousa","last_name":"Jafari","full_name":"Jafari, Atousa"},{"last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"volume":11,"title":"CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-based Pruning and Quantization","doi":"10.64552/wipiec.v11i1.99","publication_status":"published","publication_identifier":{"issn":["2980-7298","2337-0343"]},"issue":"1","year":"2025","citation":{"ieee":"A. Jafari, H. Ghasemzadeh Mohammadi, and M. Platzner, “CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-based Pruning and Quantization,” <i>WiPiEC Journal - Works in Progress in Embedded Computing Journal</i>, vol. 11, no. 1, Art. no. 4, 2025, doi: <a href=\"https://doi.org/10.64552/wipiec.v11i1.99\">10.64552/wipiec.v11i1.99</a>.","chicago":"Jafari, Atousa, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-Based Pruning and Quantization.” <i>WiPiEC Journal - Works in Progress in Embedded Computing Journal</i> 11, no. 1 (2025). <a href=\"https://doi.org/10.64552/wipiec.v11i1.99\">https://doi.org/10.64552/wipiec.v11i1.99</a>.","ama":"Jafari A, Ghasemzadeh Mohammadi H, Platzner M. CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-based Pruning and Quantization. <i>WiPiEC Journal - Works in Progress in Embedded Computing Journal</i>. 2025;11(1). doi:<a href=\"https://doi.org/10.64552/wipiec.v11i1.99\">10.64552/wipiec.v11i1.99</a>","mla":"Jafari, Atousa, et al. “CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-Based Pruning and Quantization.” <i>WiPiEC Journal - Works in Progress in Embedded Computing Journal</i>, vol. 11, no. 1, 4, MECOnet, 2025, doi:<a href=\"https://doi.org/10.64552/wipiec.v11i1.99\">10.64552/wipiec.v11i1.99</a>.","short":"A. Jafari, H. Ghasemzadeh Mohammadi, M. Platzner, WiPiEC Journal - Works in Progress in Embedded Computing Journal 11 (2025).","bibtex":"@article{Jafari_Ghasemzadeh Mohammadi_Platzner_2025, title={CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-based Pruning and Quantization}, volume={11}, DOI={<a href=\"https://doi.org/10.64552/wipiec.v11i1.99\">10.64552/wipiec.v11i1.99</a>}, number={14}, journal={WiPiEC Journal - Works in Progress in Embedded Computing Journal}, publisher={MECOnet}, author={Jafari, Atousa and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2025} }","apa":"Jafari, A., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2025). CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-based Pruning and Quantization. <i>WiPiEC Journal - Works in Progress in Embedded Computing Journal</i>, <i>11</i>(1), Article 4. <a href=\"https://doi.org/10.64552/wipiec.v11i1.99\">https://doi.org/10.64552/wipiec.v11i1.99</a>"},"intvolume":"        11","_id":"62184","user_id":"99966","article_number":"4","type":"journal_article","publication":"WiPiEC Journal - Works in Progress in Embedded Computing Journal","abstract":[{"text":"<jats:p>While reservoir computing (RC) networks offer advantages over traditional recurrent neural net- works in terms of training time and operational cost for time-series applications, deploying them on edge devices still presents significant challenges due to re- source constraints. Network compression, i.e., pruning and quantization, are thus of utmost importance. We propose a Compressed Reservoir Computing (CRC) framework that integrates advanced pruning and quantization techniques to optimize throughput, latency, energy efficiency, and resource utilization for FPGA- based RC accelerators.We describe the framework with a focus on HSIC LASSO as a novel pruning method that can capture non-linear dependencies between neurons. We validate our framework with time series classification and regression tasks, for which we generate FPGA accelerators. The accelerators achieve a very high throughput of up to 188 Megasamples/s with a latency of 5.32 ns, while reducing resource utilization by 12× and lowering the energy by 10× compared to a baseline hardware implementation, without compromising accuracy.</jats:p>","lang":"eng"}],"status":"public"}]