@inproceedings{36994,
  abstract     = {{This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP.}},
  author       = {{Xie, Tao  and Müller, Wolfgang and Letombe, Florian}},
  booktitle    = {{Proceedings of SOCC2012}},
  keywords     = {{Analytical models, Hardware design languages, Microprocessors, Cost function, Data models, Search problems, IP networks}},
  publisher    = {{IEEE}},
  title        = {{{Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}}},
  doi          = {{10.1109/SOCC.2012.6398362}},
  year         = {{2012}},
}

@inproceedings{37002,
  abstract     = {{HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.}},
  author       = {{Xie, Tao and Müller, Wolfgang and Letombe, Florian}},
  booktitle    = {{Proceedings of Euromicro DSD 2011}},
  isbn         = {{978-1-4577-1048-3}},
  keywords     = {{Hardware design languages, Cost function, Computational modeling, Fault detection, Data models, Analytical models, Testing}},
  publisher    = {{IEEE}},
  title        = {{{HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}}},
  doi          = {{10.1109/DSD.2011.83}},
  year         = {{2011}},
}

@inproceedings{37009,
  abstract     = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}},
  author       = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Assertion-Based Verification of RTOS Properties}}},
  doi          = {{10.1109/DATE.2010.5457130}},
  year         = {{2010}},
}

@inproceedings{37066,
  abstract     = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.}},
  author       = {{Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE'09}},
  isbn         = {{978-1-4244-3781-8}},
  keywords     = {{Timing, Analytical models, Clocks, Performance analysis, Scheduling, Operating systems, Delay, Real time systems, Application software, Context modeling}},
  title        = {{{Increased Accuracy through Noise Injection in Abstract RTOS Simulation}}},
  doi          = {{10.1109/DATE.2009.5090925}},
  year         = {{2009}},
}