@inproceedings{56166, abstract = {{Developing Intelligent Technical Systems (ITS) involves a complex process encompassing planning, analysis, design, production, and maintenance. Model-Based Systems Engineering (MBSE) is a key methodology for systematic systems engineering. Designing models for ITS requires harmonious interaction of various elements, posing a challenge in MBSE. Leveraging Generative Artificial Intelligence, we generated a dataset for modeling, using prompt engineering on large language models. The generated artifacts can aid engineers in MBSE design or serve as synthetic training data for AI assistants.}}, author = {{Kulkarni, Pranav Jayant and Tissen, Denis and Bernijazov, Ruslan and Dumitrescu, Roman}}, booktitle = {{DS 130: Proceedings of NordDesign 2024}}, editor = {{Malmqvist, J. and Candi, M. and Saemundsson, R. and Bystrom, F. and Isaksson, O.}}, keywords = {{Data Driven Design, Design Automation, Systems Engineering (SE), Artificial Intelligence (AI)}}, location = {{Reykjavik}}, pages = {{617--625}}, title = {{{Towards Automated Design: Automatically Generating Modeling Elements with Prompt Engineering and Generative Artificial Intelligence}}}, doi = {{10.35199/NORDDESIGN2024.66}}, year = {{2024}}, } @inbook{30290, abstract = {{The article explores the particular quality of changes introduced through the latest wave of digital transformation of workplaces. It has effects on workflow processes, on distribution of work and tasks, and the mode of distributing working tasks, e.g. through cyber-physical systems. Hence, the changes in work are manifold and require changes in vocational education and training as well as in workplace learning. These changes reveal new challenges for research on workplace learning. Finally, conclusions for future workplace learning research will be developed.}}, author = {{Harteis, Christian}}, booktitle = {{Research Approaches on Workplace Learning}}, isbn = {{9783030895815}}, issn = {{2210-5549}}, keywords = {{Digitalisation Self organisation Distribution of labour Automation}}, publisher = {{Springer International Publishing}}, title = {{{Research on Workplace Learning in Times of Digitalisation}}}, doi = {{10.1007/978-3-030-89582-2_19}}, year = {{2022}}, } @inproceedings{10577, abstract = {{State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution. In this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing.}}, author = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19}}, isbn = {{9781450362528}}, keywords = {{Approximate computing, design automation, parameter selection, circuit synthesis}}, location = {{Tysons Corner, VA, USA}}, publisher = {{ACM}}, title = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}}, doi = {{10.1145/3299874.3317998}}, year = {{2019}}, } @inproceedings{38784, abstract = {{This article presents the classification tree method for functional verification to close the gap from the specification of a test plan to SystemVerilog (Chandra and Chakrabarty, 2001) test bench generation. Our method supports the systematic development of test configurations and is based on the classification tree method for embedded systems (CTM/ES) (Chakrabarty et al., 2000) extending CTM/ES for random test generation as well as for functional coverage and property specification}}, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of the Design Automation & Test in Europe Conference}}, isbn = {{3-9810801-1-4}}, keywords = {{Classification tree analysis, System testing, Embedded system, Safety, Automatic testing, Automation}}, publisher = {{IEEE}}, title = {{{Classification Trees for Functional Coverage and Random Test Generation}}}, doi = {{10.1109/DATE.2006.243902}}, year = {{2006}}, } @inproceedings{39050, abstract = {{Currently, middleware for smart home networks with embedded and mobile devices are in the focus of several investigations. In this paper, we propose a middleware for secure management of device and user profiles by integrating a profile database with a generic authentication scheme for an X.509 enabled ticket management in the context of the OSGi framework. After the introduction of the individual system components and their interaction, we also discuss potential system attacks.}}, author = {{Ziegler, Max and Müller, Wolfgang and Schäfer, Robbie and Loeser, Chris}}, booktitle = {{Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)}}, isbn = {{0-7695-2424-9}}, keywords = {{Intelligent networks, Smart homes, Middleware, Project management, Data security, Ubiquitous computing, Context-aware services, Computer architecture, Home automation, Environmental management}}, location = {{Copenhagen, Denmark }}, publisher = {{IEEE}}, title = {{{Secure Profile Management in Smart Home Networks}}}, doi = {{10.1109/DEXA.2005.171}}, year = {{2005}}, } @inproceedings{39061, abstract = {{This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML state diagrams, which are translated to the formal B language and are model checked for real-time properties. By means of the B language and a B theorem prover, refined state diagrams are verified against their abstract representation. The approach is presented by means of the refinement of a digital echo cancellation unit.}}, author = {{Krupp, Alexander and Müller, Wolfgang and Oliver, Ian}}, booktitle = {{Proceedings of DATE’04 Designers' Forum}}, isbn = {{0-7695-2085-5}}, keywords = {{Echo cancellers, Logic, Unified modeling language, Automata, Data structures, Boolean functions, Electronic design automation and methodology, Prototypes, Specification languages, Constraint theory}}, title = {{{Formal Refinement and Model Checking of An Echo Cancellation Unit}}}, doi = {{10.1109/DATE.2004.1269214}}, year = {{2004}}, } @inproceedings{39421, abstract = {{We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.}}, author = {{Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W. and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}}, booktitle = {{Proceedings of the Design, Automation, and Test in Europe (DATE’01)}}, isbn = {{0-7695-0993-2}}, keywords = {{Yarn, Formal verification, Kernel, Hardware design languages, Electronic design automation and methodology, Algebra, Computational modeling, Logic functions, Computer languages, Clocks}}, publisher = {{IEEE}}, title = {{{The Simulation Semantics of SystemC}}}, doi = {{10.1109/DATE.2001.915002}}, year = {{2001}}, } @inproceedings{39502, abstract = {{The authors present a new approach to an interactive design and analysis environment for visual languages. The main components, i.e., editor animator and interpreter are introduced. Their interactions are being investigated emphasizing the interpreter-animator interaction and defining an interface supporting different levels of automation. The interpreter performs the executions on a logical level and triggers the animator. The interactive animation provides a very high degree of liveness since it is based on the tight integration of the animator and editor. The proposed architecture permits the distributed implementation of a system for real-time animation. Their concepts are validated by the implementation of a debugging environment for the complete visual programming language Pictorial Janus.}}, author = {{Dücker, M. and Lehrenfeld, Georg and Müller, Wolfgang and Tahedl, C.}}, booktitle = {{ Proceedings International Conference and Workshop on Engineering of Computer-Based Systems}}, isbn = {{0-8186-7889-5}}, keywords = {{Real time systems, Animation, Debugging, Automation, Computer languages, Timing, Environmental management, Programming environments, Visualization, Multimedia systems}}, location = {{Monterey, CA, USA }}, title = {{{A Generic System for Interactive Real--Time Animation}}}, doi = {{10.1109/ECBS.1997.581876}}, year = {{1997}}, }