[{"citation":{"mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }","apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>","ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>."},"year":"2010","place":"Dresden","publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"},"doi":"10.1109/DATE.2010.5456965","title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"last_name":"Di Guglielmo","full_name":"Di Guglielmo, Giuseppe","first_name":"Giuseppe"},{"first_name":"Franco","last_name":"Fummi","full_name":"Fummi, Franco"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Graziano","full_name":"Pravadelli, Graziano","last_name":"Pravadelli"},{"first_name":"Tao","full_name":"Xie, Tao","last_name":"Xie"}],"date_created":"2023-01-17T10:47:29Z","publisher":"IEEE","date_updated":"2023-01-17T10:47:37Z","status":"public","abstract":[{"text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.","lang":"eng"}],"type":"conference","publication":"Proceedings of DATE’10","language":[{"iso":"eng"}],"keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"user_id":"5786","department":[{"_id":"672"}],"_id":"37040"},{"department":[{"_id":"672"}],"series_title":"Lecture Notes in Electrical Engineering","user_id":"5786","_id":"37050","language":[{"iso":"eng"}],"keyword":["Communicate Sequential Process     Virtual Platform     Smart Camera     Synchronous Data Flow     Artisan Studio"],"publication":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI","type":"conference","status":"public","abstract":[{"lang":"eng","text":"The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of the SysML tool suite ARTiSAN Studio®. We finally discuss the evaluation of the approach by two case studies."}],"date_created":"2023-01-17T11:19:45Z","author":[{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Da","full_name":"He, Da","last_name":"He"},{"first_name":"Fabian","full_name":"Mischkalla, Fabian","last_name":"Mischkalla"},{"full_name":"Wegele, Arthur","last_name":"Wegele","first_name":"Arthur"},{"first_name":"Adrian","last_name":"Larkham","full_name":"Larkham, Adrian"},{"first_name":"Paul","full_name":"Whiston, Paul","last_name":"Whiston"},{"full_name":"Penil, Pablo","last_name":"Penil","first_name":"Pablo"},{"last_name":"Villar","full_name":"Villar, Eugenio","first_name":"Eugenio"},{"first_name":"Nikolaos","full_name":"Mitas, Nikolaos","last_name":"Mitas"},{"first_name":"Dimitros","full_name":"Kritharidis, Dimitros","last_name":"Kritharidis"},{"last_name":"Azcarate","full_name":"Azcarate, Florent","first_name":"Florent"},{"full_name":"Carballeda, Manuel","last_name":"Carballeda","first_name":"Manuel"}],"date_updated":"2023-01-17T11:19:53Z","doi":"10.1007/978-94-007-1488-5_9","title":"The SATURN Approach to SysML-based HW/SW Codesign","publication_identifier":{"eisbn":["978-94-007-1488-5"]},"citation":{"ama":"Müller W, He D, Mischkalla F, et al. The SATURN Approach to SysML-based HW/SW Codesign. In: <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. Lecture Notes in Electrical Engineering. ; 2010. doi:<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>","ieee":"W. Müller <i>et al.</i>, “The SATURN Approach to SysML-based HW/SW Codesign,” 2010, doi: <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>.","chicago":"Müller, Wolfgang, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham, Paul Whiston, Pablo Penil, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.” In <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. Lecture Notes in Electrical Engineering, 2010. <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">https://doi.org/10.1007/978-94-007-1488-5_9</a>.","apa":"Müller, W., He, D., Mischkalla, F., Wegele, A., Larkham, A., Whiston, P., Penil, P., Villar, E., Mitas, N., Kritharidis, D., Azcarate, F., &#38; Carballeda, M. (2010). The SATURN Approach to SysML-based HW/SW Codesign. <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">https://doi.org/10.1007/978-94-007-1488-5_9</a>","bibtex":"@inproceedings{Müller_He_Mischkalla_Wegele_Larkham_Whiston_Penil_Villar_Mitas_Kritharidis_et al._2010, series={Lecture Notes in Electrical Engineering}, title={The SATURN Approach to SysML-based HW/SW Codesign}, DOI={<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>}, booktitle={Proceedings of the IEEE Computer Society Annual Symposium on VLSI}, author={Müller, Wolfgang and He, Da and Mischkalla, Fabian and Wegele, Arthur and Larkham, Adrian and Whiston, Paul and Penil, Pablo and Villar, Eugenio and Mitas, Nikolaos and Kritharidis, Dimitros and et al.}, year={2010}, collection={Lecture Notes in Electrical Engineering} }","short":"W. Müller, D. He, F. Mischkalla, A. Wegele, A. Larkham, P. Whiston, P. Penil, E. Villar, N. Mitas, D. Kritharidis, F. Azcarate, M. Carballeda, in: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010.","mla":"Müller, Wolfgang, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.” <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>, 2010, doi:<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>."},"year":"2010"},{"citation":{"ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>.","ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }","mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>"},"year":"2010","place":"Dresden","publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"conference":{"location":"Dresden","name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"doi":"10.1109/DATE.2010.5456965","title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"first_name":"Giuseppe","last_name":"Di Guglielmo","full_name":"Di Guglielmo, Giuseppe"},{"first_name":"Franco","last_name":"Fummi","full_name":"Fummi, Franco"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Graziano","full_name":"Pravadelli, Graziano","last_name":"Pravadelli"},{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"}],"date_created":"2023-01-17T10:44:46Z","publisher":"IEEE","date_updated":"2025-03-12T16:39:17Z","status":"public","abstract":[{"text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.","lang":"eng"}],"type":"conference","publication":"Proceedings of DATE’10","language":[{"iso":"eng"}],"keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"user_id":"5786","_id":"37039"},{"language":[{"iso":"eng"}],"keyword":["Command and control process","Command and control systems","Design and modeling","Domain ontologies","Emergency response","Fire extinguishers","Fire protection","Heterogeneous domains","Information analysis","Information sharing","Information systems","Interoperability","Ontology language","Semantic technologies","Semantic Web","Semantics"],"user_id":"405","_id":"24065","status":"public","editor":[{"full_name":"French, Simon","last_name":"French","first_name":"Simon"},{"first_name":"Brian","full_name":"Tomaszewski, Brian","last_name":"Tomaszewski"},{"full_name":"Zobel, Chris","last_name":"Zobel","first_name":"Chris"}],"publication":"ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management","type":"conference","main_file_link":[{"url":"http://idl.iscram.org/files/pottebaum/2010/847_Pottebaum_etal2010.pdf","open_access":"1"}],"title":"Design and modeling of a domain ontology for fire protection","author":[{"first_name":"Jens","orcid":"http://orcid.org/0000-0001-8778-2989","last_name":"Pottebaum","full_name":"Pottebaum, Jens","id":"405"},{"first_name":"Anna Maria","full_name":"Japs, Anna Maria","last_name":"Japs"},{"first_name":"Stephan","full_name":"Prödel, Stephan","last_name":"Prödel"},{"full_name":"Koch, Rainer","last_name":"Koch","first_name":"Rainer"}],"date_created":"2021-09-09T12:27:14Z","date_updated":"2026-03-31T03:52:00Z","oa":"1","citation":{"chicago":"Pottebaum, Jens, Anna Maria Japs, Stephan Prödel, and Rainer Koch. “Design and Modeling of a Domain Ontology for Fire Protection.” In <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>, edited by Simon French, Brian Tomaszewski, and Chris Zobel. Seattle, WA, 2010.","ieee":"J. Pottebaum, A. M. Japs, S. Prödel, and R. Koch, “Design and modeling of a domain ontology for fire protection,” in <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>, 2010.","ama":"Pottebaum J, Japs AM, Prödel S, Koch R. Design and modeling of a domain ontology for fire protection. In: French S, Tomaszewski B, Zobel C, eds. <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>. ; 2010.","short":"J. Pottebaum, A.M. Japs, S. Prödel, R. Koch, in: S. French, B. Tomaszewski, C. Zobel (Eds.), ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management, Seattle, WA, 2010.","mla":"Pottebaum, Jens, et al. “Design and Modeling of a Domain Ontology for Fire Protection.” <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>, edited by Simon French et al., 2010.","bibtex":"@inproceedings{Pottebaum_Japs_Prödel_Koch_2010, place={Seattle, WA}, title={Design and modeling of a domain ontology for fire protection}, booktitle={ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management}, author={Pottebaum, Jens and Japs, Anna Maria and Prödel, Stephan and Koch, Rainer}, editor={French, Simon and Tomaszewski, Brian and Zobel, Chris}, year={2010} }","apa":"Pottebaum, J., Japs, A. M., Prödel, S., &#38; Koch, R. (2010). Design and modeling of a domain ontology for fire protection. In S. French, B. Tomaszewski, &#38; C. Zobel (Eds.), <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>."},"year":"2010","place":"Seattle, WA","quality_controlled":"1"},{"publication":"4th Workshop on Positioning Navigation and Communication (WPNC 2007)","type":"conference","status":"public","abstract":[{"lang":"eng","text":"In this paper, we experimentally evaluate algorithms for velocity estimation of a GSM 900 mobile terminal which are based on the analysis of the statistical properties of the fast fading process. It is shown how theses statistics can be obtained from the training sequences present in downlink transmission bursts without establishing an active connection. Realistic simulations of a GSM channel according to the COST 207 channel models have been conducted. These models incorporate effects like multipath propagation, fading, cochannel interference and additive noise. It is shown that velocity estimation by searching for the maximum slope of the power density spectrum of the fast fading performs best."}],"department":[{"_id":"54"}],"user_id":"44006","_id":"11883","language":[{"iso":"eng"}],"keyword":["additive noise","cellular radio","channel estimation","cochannel interference","COST 207 channel models","downlink transmission bursts","fading channels","fading process","GSM downlink signalling","mobile terminals","multipath channels","multipath propagation","power density spectrum","statistical analysis","statistical properties","telecommunication links","telecommunication terminals","velocity estimation"],"page":"217-222","citation":{"short":"S. Peschke, R. Haeb-Umbach, in: 4th Workshop on Positioning Navigation and Communication (WPNC 2007), 2007, pp. 217–222.","bibtex":"@inproceedings{Peschke_Haeb-Umbach_2007, title={Velocity Estimation of Mobile Terminals by Exploiting GSM Downlink Signalling}, DOI={<a href=\"https://doi.org/10.1109/WPNC.2007.353637\">10.1109/WPNC.2007.353637</a>}, booktitle={4th Workshop on Positioning Navigation and Communication (WPNC 2007)}, author={Peschke, Sven and Haeb-Umbach, Reinhold}, year={2007}, pages={217–222} }","mla":"Peschke, Sven, and Reinhold Haeb-Umbach. “Velocity Estimation of Mobile Terminals by Exploiting GSM Downlink Signalling.” <i>4th Workshop on Positioning Navigation and Communication (WPNC 2007)</i>, 2007, pp. 217–22, doi:<a href=\"https://doi.org/10.1109/WPNC.2007.353637\">10.1109/WPNC.2007.353637</a>.","apa":"Peschke, S., &#38; Haeb-Umbach, R. (2007). Velocity Estimation of Mobile Terminals by Exploiting GSM Downlink Signalling. In <i>4th Workshop on Positioning Navigation and Communication (WPNC 2007)</i> (pp. 217–222). <a href=\"https://doi.org/10.1109/WPNC.2007.353637\">https://doi.org/10.1109/WPNC.2007.353637</a>","chicago":"Peschke, Sven, and Reinhold Haeb-Umbach. “Velocity Estimation of Mobile Terminals by Exploiting GSM Downlink Signalling.” In <i>4th Workshop on Positioning Navigation and Communication (WPNC 2007)</i>, 217–22, 2007. <a href=\"https://doi.org/10.1109/WPNC.2007.353637\">https://doi.org/10.1109/WPNC.2007.353637</a>.","ieee":"S. Peschke and R. Haeb-Umbach, “Velocity Estimation of Mobile Terminals by Exploiting GSM Downlink Signalling,” in <i>4th Workshop on Positioning Navigation and Communication (WPNC 2007)</i>, 2007, pp. 217–222.","ama":"Peschke S, Haeb-Umbach R. Velocity Estimation of Mobile Terminals by Exploiting GSM Downlink Signalling. In: <i>4th Workshop on Positioning Navigation and Communication (WPNC 2007)</i>. ; 2007:217-222. doi:<a href=\"https://doi.org/10.1109/WPNC.2007.353637\">10.1109/WPNC.2007.353637</a>"},"year":"2007","date_created":"2019-07-12T05:30:06Z","author":[{"last_name":"Peschke","full_name":"Peschke, Sven","first_name":"Sven"},{"last_name":"Haeb-Umbach","full_name":"Haeb-Umbach, Reinhold","id":"242","first_name":"Reinhold"}],"date_updated":"2022-01-06T06:51:11Z","oa":"1","doi":"10.1109/WPNC.2007.353637","main_file_link":[{"url":"https://groups.uni-paderborn.de/nt/pubs/2007/PeHa07.pdf","open_access":"1"}],"title":"Velocity Estimation of Mobile Terminals by Exploiting GSM Downlink Signalling"},{"publication":"Proceedings of IEEE KMN 2001","type":"conference","status":"public","abstract":[{"lang":"eng","text":"Rapid prototyping based on 3D models is well accepted for several applications. This article addresses the application of animated virtual 3D prototypes for the development of computer-based systems supporting early collaboration of the system designer with the external customer. Our methodology seamlessly integrates illustration through 3D animation with the main tasks of computer-based real-time systems development, i.e., implementation and verification. The approach is outlined by the example of the design of a flexible manufacturing system."}],"department":[{"_id":"672"}],"user_id":"5786","_id":"39411","language":[{"iso":"eng"}],"keyword":["Virtual prototyping","Animation","Collaboration","System analysis and design","Feedback","Application software","Power system modeling","Handicapped aids","Process design","Contracts"],"publication_identifier":{"isbn":["0-7695-1269-0"]},"citation":{"ieee":"S. Flake, C. Geiger, W. Müller, and J. Ruf, “Customer-Oriented Systems Design through Virtual Prototyps,” presented at the Proceedings Tenth IEEE International Workshop on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2001, doi: <a href=\"https://doi.org/10.1109/ENABL.2001.953425\">10.1109/ENABL.2001.953425</a>.","chicago":"Flake, Stephan, Christian Geiger, Wolfgang Müller, and Jürgen Ruf. “Customer-Oriented Systems Design through Virtual Prototyps.” In <i>Proceedings of IEEE KMN 2001</i>. Cambridge, MA, USA , 2001. <a href=\"https://doi.org/10.1109/ENABL.2001.953425\">https://doi.org/10.1109/ENABL.2001.953425</a>.","ama":"Flake S, Geiger C, Müller W, Ruf J. Customer-Oriented Systems Design through Virtual Prototyps. In: <i>Proceedings of IEEE KMN 2001</i>. ; 2001. doi:<a href=\"https://doi.org/10.1109/ENABL.2001.953425\">10.1109/ENABL.2001.953425</a>","mla":"Flake, Stephan, et al. “Customer-Oriented Systems Design through Virtual Prototyps.” <i>Proceedings of IEEE KMN 2001</i>, 2001, doi:<a href=\"https://doi.org/10.1109/ENABL.2001.953425\">10.1109/ENABL.2001.953425</a>.","bibtex":"@inproceedings{Flake_Geiger_Müller_Ruf_2001, place={Cambridge, MA, USA }, title={Customer-Oriented Systems Design through Virtual Prototyps}, DOI={<a href=\"https://doi.org/10.1109/ENABL.2001.953425\">10.1109/ENABL.2001.953425</a>}, booktitle={Proceedings of IEEE KMN 2001}, author={Flake, Stephan and Geiger, Christian and Müller, Wolfgang and Ruf, Jürgen}, year={2001} }","short":"S. Flake, C. Geiger, W. Müller, J. Ruf, in: Proceedings of IEEE KMN 2001, Cambridge, MA, USA , 2001.","apa":"Flake, S., Geiger, C., Müller, W., &#38; Ruf, J. (2001). Customer-Oriented Systems Design through Virtual Prototyps. <i>Proceedings of IEEE KMN 2001</i>. Proceedings Tenth IEEE International Workshop on Enabling Technologies: Infrastructure for Collaborative Enterprises. <a href=\"https://doi.org/10.1109/ENABL.2001.953425\">https://doi.org/10.1109/ENABL.2001.953425</a>"},"year":"2001","place":"Cambridge, MA, USA ","date_created":"2023-01-24T10:30:14Z","author":[{"first_name":"Stephan","last_name":"Flake","full_name":"Flake, Stephan"},{"first_name":"Christian","last_name":"Geiger","full_name":"Geiger, Christian"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Ruf, Jürgen","last_name":"Ruf","first_name":"Jürgen"}],"date_updated":"2023-01-24T10:30:21Z","doi":"10.1109/ENABL.2001.953425","conference":{"name":"Proceedings Tenth IEEE International Workshop on Enabling Technologies: Infrastructure for Collaborative Enterprises"},"title":"Customer-Oriented Systems Design through Virtual Prototyps"},{"status":"public","abstract":[{"text":"This article introduces and discusses different innovative means for visual specification and animation of complex concurrent systems. It introduces the completely visual programming language Pictorial Janus (PJ) and its application in the customer-oriented design process. PJ implements a completely visual programming language with inherent animation facilities. The article outlines the transformation of purely visual PJ programs into textual imperative programming languages. The second part of the article investigates animated 3D-presentations and introduces a novel approach to an animated 3D programming language for interactive customer-oriented illustrations.","lang":"eng"}],"type":"conference","publication":"Proceedings of HICSS-32","language":[{"iso":"eng"}],"keyword":["Animation","Computer languages","Object oriented modeling","Collaboration","Process design","Graphical user interfaces","Jacobian matrices","Standardization","Feedback","Software prototyping"],"user_id":"5786","department":[{"_id":"672"}],"_id":"39487","citation":{"mla":"Geiger, Christian, et al. “Visual Specification, Modeling, and Illustrations of Complex Systems.” <i>Proceedings of HICSS-32</i>, 1999, doi:<a href=\"https://doi.org/10.1109/HICSS.1999.772621\">10.1109/HICSS.1999.772621</a>.","short":"C. Geiger, G. Lehrenfeld, W. Müller, in: Proceedings of HICSS-32, Maui, Hawaii, 1999.","bibtex":"@inproceedings{Geiger_Lehrenfeld_Müller_1999, place={Maui, Hawaii}, title={Visual Specification, Modeling, and Illustrations of Complex Systems}, DOI={<a href=\"https://doi.org/10.1109/HICSS.1999.772621\">10.1109/HICSS.1999.772621</a>}, booktitle={Proceedings of HICSS-32}, author={Geiger, Christian and Lehrenfeld, G. and Müller, Wolfgang}, year={1999} }","apa":"Geiger, C., Lehrenfeld, G., &#38; Müller, W. (1999). Visual Specification, Modeling, and Illustrations of Complex Systems. <i>Proceedings of HICSS-32</i>. Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences 1999, Maui, Hawaii. <a href=\"https://doi.org/10.1109/HICSS.1999.772621\">https://doi.org/10.1109/HICSS.1999.772621</a>","ama":"Geiger C, Lehrenfeld G, Müller W. Visual Specification, Modeling, and Illustrations of Complex Systems. In: <i>Proceedings of HICSS-32</i>. ; 1999. doi:<a href=\"https://doi.org/10.1109/HICSS.1999.772621\">10.1109/HICSS.1999.772621</a>","chicago":"Geiger, Christian, G. Lehrenfeld, and Wolfgang Müller. “Visual Specification, Modeling, and Illustrations of Complex Systems.” In <i>Proceedings of HICSS-32</i>. Maui, Hawaii, 1999. <a href=\"https://doi.org/10.1109/HICSS.1999.772621\">https://doi.org/10.1109/HICSS.1999.772621</a>.","ieee":"C. Geiger, G. Lehrenfeld, and W. Müller, “Visual Specification, Modeling, and Illustrations of Complex Systems,” presented at the Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences 1999, Maui, Hawaii, 1999, doi: <a href=\"https://doi.org/10.1109/HICSS.1999.772621\">10.1109/HICSS.1999.772621</a>."},"place":"Maui, Hawaii","year":"1999","publication_identifier":{"isbn":["0-7695-0001-3"]},"doi":"10.1109/HICSS.1999.772621","conference":{"location":"Maui, Hawaii","name":"Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences 1999"},"title":"Visual Specification, Modeling, and Illustrations of Complex Systems","date_created":"2023-01-24T11:33:05Z","author":[{"first_name":"Christian","last_name":"Geiger","full_name":"Geiger, Christian"},{"full_name":"Lehrenfeld, G.","last_name":"Lehrenfeld","first_name":"G."},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"date_updated":"2023-01-24T11:33:35Z"},{"place":"Dordrecht","year":"1995","page":"107 - 139","citation":{"apa":"Börger, E., Glässer, U., &#38; Müller, W. (1995). A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines. In C. Delgado Kloos &#38; P. T. Breuer (Eds.), <i>Semantics of VHDL</i> (pp. 107–139). Kluwer Academic Publishers. <a href=\"https://doi.org/10.1007/978-1-4615-2237-9_5\">https://doi.org/10.1007/978-1-4615-2237-9_5</a>","mla":"Börger, Egon, et al. “A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines.” <i>Semantics of VHDL</i>, edited by C. Delgado Kloos and Peter T. Breuer, Kluwer Academic Publishers, 1995, pp. 107–39, doi:<a href=\"https://doi.org/10.1007/978-1-4615-2237-9_5\">10.1007/978-1-4615-2237-9_5</a>.","bibtex":"@inbook{Börger_Glässer_Müller_1995, place={Dordrecht}, title={A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines}, DOI={<a href=\"https://doi.org/10.1007/978-1-4615-2237-9_5\">10.1007/978-1-4615-2237-9_5</a>}, booktitle={Semantics of VHDL}, publisher={Kluwer Academic Publishers}, author={Börger, Egon and Glässer, Uwe and Müller, Wolfgang}, editor={Delgado Kloos, C. and Breuer, Peter T.}, year={1995}, pages={107–139} }","short":"E. Börger, U. Glässer, W. Müller, in: C. Delgado Kloos, P.T. Breuer (Eds.), Semantics of VHDL, Kluwer Academic Publishers, Dordrecht, 1995, pp. 107–139.","ama":"Börger E, Glässer U, Müller W. A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines. In: Delgado Kloos C, Breuer PT, eds. <i>Semantics of VHDL</i>. Kluwer Academic Publishers; 1995:107-139. doi:<a href=\"https://doi.org/10.1007/978-1-4615-2237-9_5\">10.1007/978-1-4615-2237-9_5</a>","chicago":"Börger, Egon, Uwe Glässer, and Wolfgang Müller. “A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines.” In <i>Semantics of VHDL</i>, edited by C. Delgado Kloos and Peter T. Breuer, 107–39. Dordrecht: Kluwer Academic Publishers, 1995. <a href=\"https://doi.org/10.1007/978-1-4615-2237-9_5\">https://doi.org/10.1007/978-1-4615-2237-9_5</a>.","ieee":"E. Börger, U. Glässer, and W. Müller, “A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines,” in <i>Semantics of VHDL</i>, C. Delgado Kloos and P. T. Breuer, Eds. Dordrecht: Kluwer Academic Publishers, 1995, pp. 107–139."},"publication_identifier":{"isbn":["978-1-4615-2237-9"]},"title":"A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines","doi":"10.1007/978-1-4615-2237-9_5","date_updated":"2022-12-15T11:43:14Z","publisher":"Kluwer Academic Publishers","date_created":"2022-12-15T11:42:48Z","author":[{"full_name":"Börger, Egon","last_name":"Börger","first_name":"Egon"},{"first_name":"Uwe","full_name":"Glässer, Uwe","last_name":"Glässer"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"abstract":[{"lang":"eng","text":"We present a rigorous but transparent semantic definition for VHDL corresponding to the IEEE VHDL’ 93 standard [68, 9, 84]. Our definition covers the full behavior of signal and variable assignments as well as the behavior of the various wait statements including delta, time, and postponed cycles. We consider explicitly declared signals, ports, local variables, and shared variables. Our specification defines an abstract VHDL ’ 93 interpreter in the form of transition rules for an evolving algebra machine (EA-Machine) [60]. It faithfully reflects and supports the view of simulation given in the IEEE VHDL ’ 93 standard language reference manual. The definition can be understood without any prior formal training. We illustrate our definition by running the example VHDL program set out in the Introduction to this volume."}],"editor":[{"full_name":"Delgado Kloos, C.","last_name":"Delgado Kloos","first_name":"C."},{"first_name":"Peter T.","full_name":"Breuer, Peter T.","last_name":"Breuer"}],"status":"public","publication":"Semantics of VHDL","type":"book_chapter","keyword":["Transition Rule     Formal Verification     Variable Assignment     Kernel Process     Simulation Cycle"],"language":[{"iso":"eng"}],"_id":"34448","department":[{"_id":"672"}],"user_id":"5786"}]