---
_id: '63758'
abstract:
- lang: eng
  text: Resilient systems require monitoring and prediction of environmental and intrinsic
    conditions and the ability to adapt to changing circumstances to optimize the
    trade-off between performance, power consumption, and fault tolerance. TETRISC
    was introduced as a resilient multicore RISC-V processor system based on the PULPissimo
    platform. This paper presents the migration of TETRISC to the Rocket Chip SoC,
    which is freely scalable to the number of processors through parametrizable Chisel
    models. As such, we discuss and evaluate the main advantages and obstacles that
    come with the Chipyard framework for RTL simulation and FPGA synthesis for the
    rapid prototyping of resilient, scalable architectures that are online configurable
    through software for different multicore and lock-step modes.
author:
- first_name: Kai Arne
  full_name: Hannemann, Kai Arne
  id: '63972'
  last_name: Hannemann
- first_name: Lars
  full_name: Luchterhandt, Lars
  last_name: Luchterhandt
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Markus
  full_name: Ulbricht, Markus
  last_name: Ulbricht
- first_name: Li
  full_name: Lu, Li
  last_name: Lu
citation:
  ama: 'Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L. Redesigning the
    TETRISC Architecture for Scalable Rocket Chip Implementations. In: <i>38. ITG
    / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>.
    ; 2026.'
  apa: Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., &#38; Lu, L.
    (2026). Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.
    <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen
    Und Systemen</i>. 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit
    von Schaltungen und Systemen, Potsdam.
  bibtex: '@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_2026, place={Potsdam},
    title={Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations},
    booktitle={38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von
    Schaltungen und Systemen}, author={Hannemann, Kai Arne and Luchterhandt, Lars
    and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}, year={2026} }'
  chicago: Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht,
    and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.”
    In <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen
    Und Systemen</i>. Potsdam, 2026.
  ieee: K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning
    the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented
    at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
    und Systemen, Potsdam, 2026.
  mla: Hannemann, Kai Arne, et al. “Redesigning the TETRISC Architecture for Scalable
    Rocket Chip Implementations.” <i>38. ITG / GMM / GI - Workshop Testmethoden Und
    Zuverlässigkeit von Schaltungen Und Systemen</i>, 2026.
  short: 'K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, in: 38.
    ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und
    Systemen, Potsdam, 2026.'
conference:
  end_date: 2026-02-24
  location: Potsdam
  name: 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
    und Systemen
  start_date: 2026-02-22
date_created: 2026-01-27T13:14:51Z
date_updated: 2026-05-08T09:08:14Z
department:
- _id: '58'
has_accepted_license: '1'
keyword:
- RISC-V
- Multicore
- Fault Tolerant
- TETRISC
- Chisel
- Chipyard
language:
- iso: eng
place: Potsdam
publication: 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
  und Systemen
status: public
title: Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations
type: conference
user_id: '63972'
year: '2026'
...