@inproceedings{36919,
  abstract     = {{Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a "loosely-timed" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability.}},
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  keywords     = {{Time-varying systems, Time-domain analysis, Synchronization, Context modeling, Clocks, Semantics, Standards}},
  publisher    = {{IEEE}},
  title        = {{{Efficient Power-Intent Validation Using "Loosely-Timed" Simulation Models: A Non-Invasive Approach}}},
  doi          = {{10.1109/PATMOS.2013.6662171}},
  year         = {{2013}},
}

@inproceedings{37040,
  abstract     = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}},
  author       = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}},
  doi          = {{10.1109/DATE.2010.5456965}},
  year         = {{2010}},
}

@inproceedings{37039,
  abstract     = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}},
  author       = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}},
  doi          = {{10.1109/DATE.2010.5456965}},
  year         = {{2010}},
}

@inproceedings{37066,
  abstract     = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.}},
  author       = {{Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE'09}},
  isbn         = {{978-1-4244-3781-8}},
  keywords     = {{Timing, Analytical models, Clocks, Performance analysis, Scheduling, Operating systems, Delay, Real time systems, Application software, Context modeling}},
  title        = {{{Increased Accuracy through Noise Injection in Abstract RTOS Simulation}}},
  doi          = {{10.1109/DATE.2009.5090925}},
  year         = {{2009}},
}

@inproceedings{39505,
  abstract     = {{3D-graphics are becoming popular in a steadily increasing number of areas such as entertainment, scientific visualization, simulation, and virtual reality. Despite this rapid growth the generation of animated 3D scenes is by no means trivial. Since animated 3D objects evolve over time the authors denote these objects as 4D. The article presents a novel approach to the rapid prototyping of 4D models. They introduce the AAL (Animated Agent Layer) system. AAL is an interpreter-based approach covering a textual (AAL-PR) as well as a visual command language (AAL-VL) for the specification of the dynamics in 4D scenes. AAL provides support for different levels of abstraction: primitives, structured objects, animated objects, and animated (autonomous) agents.}},
  author       = {{Dücker, M. and Geiger, Christian and Hunstock, R. and Lehrenfeld, Georg and Müller, Wolfgang}},
  booktitle    = {{Proceedings of the 1997 IEEE Symposium on Visual Languages}},
  isbn         = {{0-8186-8144-6}},
  keywords     = {{Prototypes, Layout, Animation, Command languages, Application software, Libraries, Virtual reality, Computer graphics, Hardware, Context modeling}},
  title        = {{{Visual-Textual Prototyping of 4D Scenes}}},
  doi          = {{10.1109/VL.1997.626601}},
  year         = {{1997}},
}

@inproceedings{39538,
  abstract     = {{This article discusses the application of Pictorial Janus (PJ) for the rapid development and analysis of protocols by animation and complete visualization. In order to make PJ applicable in the context of hardware description we first extend PJ by timing facilities (Timed PJ) and introduce an approach for integrating VHDL models into this visual framework preserving the simulation semantics of VHDL. We finally give the example of the specification and animation of a non interlocked protocol.}},
  author       = {{Müller, Wolfgang and Lehrenfeld, Georg and Tahedl, C.}},
  booktitle    = {{Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair}},
  isbn         = {{4-930813-67-0}},
  keywords     = {{Animation, Protocols, Timing, Computer languages, Electronic mail, Context modeling, Visualization, Control systems, Flow graphs, Trademarks}},
  title        = {{{Complete Visual Specification and Animations of Protocols}}},
  doi          = {{10.1109/ASPDAC.1995.486383}},
  year         = {{1995}},
}