---
_id: '36919'
abstract:
- lang: eng
  text: Faced with increasing demands on energy efficiency, current electronic systems
    operate according to complex power management schemes including more and more
    fine-grained voltage frequency scaling and power shutdown scenarios. Consequently,
    validation of the power design intent should begin as early as possible at electronic
    system-level (ESL) together with first executable system specifications for integrity
    tests. However, today's system-level design methodologies usually focus on the
    abstraction of digital logic and time, so that typical low-power aspects cannot
    be considered so far. In this paper, we present a high-level modeling approach
    on top of the SystemC/TLM standard to simulate power distribution and voltage
    based implications in a "loosely-timed" functional execution context. The approach
    reuses legacy TLM models and prevents the need for detailed lock-step process
    synchronization in contrast to existing methods. A case study derived from an
    open source low-power design demonstrates the efficiency of our approach in terms
    of simulation performance and testability.
author:
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Mischkalla F, Müller W. Efficient Power-Intent Validation Using “Loosely-Timed”
    Simulation Models: A Non-Invasive Approach. In: IEEE; 2013. doi:<a href="https://doi.org/10.1109/PATMOS.2013.6662171">10.1109/PATMOS.2013.6662171</a>'
  apa: 'Mischkalla, F., &#38; Müller, W. (2013). <i>Efficient Power-Intent Validation
    Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. 23rd International
    Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). <a
    href="https://doi.org/10.1109/PATMOS.2013.6662171">https://doi.org/10.1109/PATMOS.2013.6662171</a>'
  bibtex: '@inproceedings{Mischkalla_Müller_2013, place={Karlsruhe}, title={Efficient
    Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive
    Approach}, DOI={<a href="https://doi.org/10.1109/PATMOS.2013.6662171">10.1109/PATMOS.2013.6662171</a>},
    publisher={IEEE}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2013}
    }'
  chicago: 'Mischkalla, Fabian, and Wolfgang Müller. “Efficient Power-Intent Validation
    Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach.” Karlsruhe:
    IEEE, 2013. <a href="https://doi.org/10.1109/PATMOS.2013.6662171">https://doi.org/10.1109/PATMOS.2013.6662171</a>.'
  ieee: 'F. Mischkalla and W. Müller, “Efficient Power-Intent Validation Using ‘Loosely-Timed’
    Simulation Models: A Non-Invasive Approach,” presented at the 23rd International
    Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013,
    doi: <a href="https://doi.org/10.1109/PATMOS.2013.6662171">10.1109/PATMOS.2013.6662171</a>.'
  mla: 'Mischkalla, Fabian, and Wolfgang Müller. <i>Efficient Power-Intent Validation
    Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. IEEE, 2013,
    doi:<a href="https://doi.org/10.1109/PATMOS.2013.6662171">10.1109/PATMOS.2013.6662171</a>.'
  short: 'F. Mischkalla, W. Müller, in: IEEE, Karlsruhe, 2013.'
conference:
  name: 23rd International Workshop on Power and Timing Modeling, Optimization and
    Simulation (PATMOS)
date_created: 2023-01-16T12:08:03Z
date_updated: 2023-01-16T12:08:17Z
department:
- _id: '672'
doi: 10.1109/PATMOS.2013.6662171
keyword:
- Time-varying systems
- Time-domain analysis
- Synchronization
- Context modeling
- Clocks
- Semantics
- Standards
language:
- iso: eng
place: Karlsruhe
publication_identifier:
  eisbn:
  - 978-1-4799-1170-7
publisher: IEEE
status: public
title: 'Efficient Power-Intent Validation Using "Loosely-Timed" Simulation Models:
  A Non-Invasive Approach'
type: conference
user_id: '5786'
year: '2013'
...
---
_id: '37040'
abstract:
- lang: eng
  text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
    step design process which is a trade-off between timing accuracy of the used models
    and correct estimation of the final timing performance. The use of an RTOS on
    the target platform is mandatory in the case real-time properties must be guaranteed.
    Thus, the question is when the RTOS must be introduced in this step by step refinement
    process. This paper proposes a four-level RTOS-aware refinement methodology that,
    starting from an untimed TLM SystemC description of the whole system, progressively
    introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
    till to obtain an accurate model of the final platform, where SW tasks run upon
    an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
    Each refinement level allows the designer to estimate more and more accurate timing
    properties, thus anticipating design decisions without being constrained to leave
    timing analysis to the final step of the refinement. The effectiveness of the
    methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Giuseppe
  full_name: Di Guglielmo, Giuseppe
  last_name: Di Guglielmo
- first_name: Franco
  full_name: Fummi, Franco
  last_name: Fummi
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Graziano
  full_name: Pravadelli, Graziano
  last_name: Pravadelli
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
citation:
  ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
    Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>'
  apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38;
    Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings
    of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>
  bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
    title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
    Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
    Graziano and Xie, Tao}, year={2010} }'
  chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
    Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
    Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>.'
  ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
    “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
    Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden,
    2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.'
  mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.
  short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
    in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:47:29Z
date_updated: 2023-01-17T10:47:37Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37039'
abstract:
- lang: eng
  text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
    step design process which is a trade-off between timing accuracy of the used models
    and correct estimation of the final timing performance. The use of an RTOS on
    the target platform is mandatory in the case real-time properties must be guaranteed.
    Thus, the question is when the RTOS must be introduced in this step by step refinement
    process. This paper proposes a four-level RTOS-aware refinement methodology that,
    starting from an untimed TLM SystemC description of the whole system, progressively
    introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
    till to obtain an accurate model of the final platform, where SW tasks run upon
    an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
    Each refinement level allows the designer to estimate more and more accurate timing
    properties, thus anticipating design decisions without being constrained to leave
    timing analysis to the final step of the refinement. The effectiveness of the
    methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Giuseppe
  full_name: Di Guglielmo, Giuseppe
  last_name: Di Guglielmo
- first_name: Franco
  full_name: Fummi, Franco
  last_name: Fummi
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Graziano
  full_name: Pravadelli, Graziano
  last_name: Pravadelli
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
citation:
  ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
    Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>'
  apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38;
    Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings
    of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>
  bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
    title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
    Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
    Graziano and Xie, Tao}, year={2010} }'
  chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
    Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
    Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>.'
  ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
    “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
    Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden,
    2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.'
  mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.
  short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
    in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:44:46Z
date_updated: 2025-03-12T16:39:17Z
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37066'
abstract:
- lang: eng
  text: Today, mobile and embedded real-time systems have to cope with the migration
    and allocation of multiple software tasks running on top of a real-time operating
    system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations
    and timing analysis applies for fast and early estimation to configure it towards
    the individual needs of the application and environment. In this context, a high
    accuracy of the simulation compared to an instruction set simulation (ISS) is
    of key importance. In this paper, we investigate the accuracy of abstract RTOS
    simulation and compare it to ISS and the behavior of the physical system. We show
    that we can reach an increased accuracy of the simulation when we inject noise
    into the time model. Our results indicate that it is sufficient to inject uniformly
    distributed random time values to the RTOS real-time clock.
author:
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Zabel H, Müller W. Increased Accuracy through Noise Injection in Abstract
    RTOS Simulation. In: <i>Proceedings of DATE’09</i>. ; 2009. doi:<a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>'
  apa: Zabel, H., &#38; Müller, W. (2009). Increased Accuracy through Noise Injection
    in Abstract RTOS Simulation. <i>Proceedings of DATE’09</i>. Design, Automation
    &#38; Test in Europe Conference &#38; Exhibition. <a href="https://doi.org/10.1109/DATE.2009.5090925">https://doi.org/10.1109/DATE.2009.5090925</a>
  bibtex: '@inproceedings{Zabel_Müller_2009, place={Nice, France}, title={Increased
    Accuracy through Noise Injection in Abstract RTOS Simulation}, DOI={<a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>},
    booktitle={Proceedings of DATE’09}, author={Zabel, Henning and Müller, Wolfgang},
    year={2009} }'
  chicago: Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise
    Injection in Abstract RTOS Simulation.” In <i>Proceedings of DATE’09</i>. Nice,
    France, 2009. <a href="https://doi.org/10.1109/DATE.2009.5090925">https://doi.org/10.1109/DATE.2009.5090925</a>.
  ieee: 'H. Zabel and W. Müller, “Increased Accuracy through Noise Injection in Abstract
    RTOS Simulation,” presented at the Design, Automation &#38; Test in Europe Conference
    &#38; Exhibition, 2009, doi: <a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>.'
  mla: Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise Injection
    in Abstract RTOS Simulation.” <i>Proceedings of DATE’09</i>, 2009, doi:<a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>.
  short: 'H. Zabel, W. Müller, in: Proceedings of DATE’09, Nice, France, 2009.'
conference:
  name: Design, Automation & Test in Europe Conference & Exhibition
date_created: 2023-01-17T11:51:44Z
date_updated: 2023-01-17T11:51:48Z
department:
- _id: '672'
doi: 10.1109/DATE.2009.5090925
keyword:
- Timing
- Analytical models
- Clocks
- Performance analysis
- Scheduling
- Operating systems
- Delay
- Real time systems
- Application software
- Context modeling
language:
- iso: eng
place: Nice, France
publication: Proceedings of DATE'09
publication_identifier:
  isbn:
  - 978-1-4244-3781-8
status: public
title: Increased Accuracy through Noise Injection in Abstract RTOS Simulation
type: conference
user_id: '5786'
year: '2009'
...
---
_id: '39505'
abstract:
- lang: eng
  text: '3D-graphics are becoming popular in a steadily increasing number of areas
    such as entertainment, scientific visualization, simulation, and virtual reality.
    Despite this rapid growth the generation of animated 3D scenes is by no means
    trivial. Since animated 3D objects evolve over time the authors denote these objects
    as 4D. The article presents a novel approach to the rapid prototyping of 4D models.
    They introduce the AAL (Animated Agent Layer) system. AAL is an interpreter-based
    approach covering a textual (AAL-PR) as well as a visual command language (AAL-VL)
    for the specification of the dynamics in 4D scenes. AAL provides support for different
    levels of abstraction: primitives, structured objects, animated objects, and animated
    (autonomous) agents.'
author:
- first_name: M.
  full_name: Dücker, M.
  last_name: Dücker
- first_name: Christian
  full_name: Geiger, Christian
  last_name: Geiger
- first_name: R.
  full_name: Hunstock, R.
  last_name: Hunstock
- first_name: Georg
  full_name: Lehrenfeld, Georg
  last_name: Lehrenfeld
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Dücker M, Geiger C, Hunstock R, Lehrenfeld G, Müller W. Visual-Textual Prototyping
    of 4D Scenes. In: <i>Proceedings of the 1997 IEEE Symposium on Visual Languages</i>.
    ; 1997. doi:<a href="https://doi.org/10.1109/VL.1997.626601">10.1109/VL.1997.626601</a>'
  apa: Dücker, M., Geiger, C., Hunstock, R., Lehrenfeld, G., &#38; Müller, W. (1997).
    Visual-Textual Prototyping of 4D Scenes. <i>Proceedings of the 1997 IEEE Symposium
    on Visual Languages</i>. 1997 IEEE Symposium on Visual Languages. <a href="https://doi.org/10.1109/VL.1997.626601">https://doi.org/10.1109/VL.1997.626601</a>
  bibtex: '@inproceedings{Dücker_Geiger_Hunstock_Lehrenfeld_Müller_1997, place={Capri,
    Italy}, title={Visual-Textual Prototyping of 4D Scenes}, DOI={<a href="https://doi.org/10.1109/VL.1997.626601">10.1109/VL.1997.626601</a>},
    booktitle={Proceedings of the 1997 IEEE Symposium on Visual Languages}, author={Dücker,
    M. and Geiger, Christian and Hunstock, R. and Lehrenfeld, Georg and Müller, Wolfgang},
    year={1997} }'
  chicago: Dücker, M., Christian Geiger, R. Hunstock, Georg Lehrenfeld, and Wolfgang
    Müller. “Visual-Textual Prototyping of 4D Scenes.” In <i>Proceedings of the 1997
    IEEE Symposium on Visual Languages</i>. Capri, Italy, 1997. <a href="https://doi.org/10.1109/VL.1997.626601">https://doi.org/10.1109/VL.1997.626601</a>.
  ieee: 'M. Dücker, C. Geiger, R. Hunstock, G. Lehrenfeld, and W. Müller, “Visual-Textual
    Prototyping of 4D Scenes,” presented at the 1997 IEEE Symposium on Visual Languages,
    1997, doi: <a href="https://doi.org/10.1109/VL.1997.626601">10.1109/VL.1997.626601</a>.'
  mla: Dücker, M., et al. “Visual-Textual Prototyping of 4D Scenes.” <i>Proceedings
    of the 1997 IEEE Symposium on Visual Languages</i>, 1997, doi:<a href="https://doi.org/10.1109/VL.1997.626601">10.1109/VL.1997.626601</a>.
  short: 'M. Dücker, C. Geiger, R. Hunstock, G. Lehrenfeld, W. Müller, in: Proceedings
    of the 1997 IEEE Symposium on Visual Languages, Capri, Italy, 1997.'
conference:
  name: 1997 IEEE Symposium on Visual Languages
date_created: 2023-01-24T11:48:57Z
date_updated: 2023-01-24T11:49:01Z
department:
- _id: '672'
doi: 10.1109/VL.1997.626601
keyword:
- Prototypes
- Layout
- Animation
- Command languages
- Application software
- Libraries
- Virtual reality
- Computer graphics
- Hardware
- Context modeling
language:
- iso: eng
place: Capri, Italy
publication: Proceedings of the 1997 IEEE Symposium on Visual Languages
publication_identifier:
  isbn:
  - 0-8186-8144-6
status: public
title: Visual-Textual Prototyping of 4D Scenes
type: conference
user_id: '5786'
year: '1997'
...
---
_id: '39538'
abstract:
- lang: eng
  text: This article discusses the application of Pictorial Janus (PJ) for the rapid
    development and analysis of protocols by animation and complete visualization.
    In order to make PJ applicable in the context of hardware description we first
    extend PJ by timing facilities (Timed PJ) and introduce an approach for integrating
    VHDL models into this visual framework preserving the simulation semantics of
    VHDL. We finally give the example of the specification and animation of a non
    interlocked protocol.
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Georg
  full_name: Lehrenfeld, Georg
  last_name: Lehrenfeld
- first_name: C.
  full_name: Tahedl, C.
  last_name: Tahedl
citation:
  ama: 'Müller W, Lehrenfeld G, Tahedl C. Complete Visual Specification and Animations
    of Protocols. In: <i>Proceedings of ASP-DAC’95/CHDL’95/VLSI’95 with EDA Technofair</i>.
    ; 1995. doi:<a href="https://doi.org/10.1109/ASPDAC.1995.486383">10.1109/ASPDAC.1995.486383</a>'
  apa: Müller, W., Lehrenfeld, G., &#38; Tahedl, C. (1995). Complete Visual Specification
    and Animations of Protocols. <i>Proceedings of ASP-DAC’95/CHDL’95/VLSI’95 with
    EDA Technofair</i>. <a href="https://doi.org/10.1109/ASPDAC.1995.486383">https://doi.org/10.1109/ASPDAC.1995.486383</a>
  bibtex: '@inproceedings{Müller_Lehrenfeld_Tahedl_1995, place={Chiba, Japan }, title={Complete
    Visual Specification and Animations of Protocols}, DOI={<a href="https://doi.org/10.1109/ASPDAC.1995.486383">10.1109/ASPDAC.1995.486383</a>},
    booktitle={Proceedings of ASP-DAC’95/CHDL’95/VLSI’95 with EDA Technofair}, author={Müller,
    Wolfgang and Lehrenfeld, Georg and Tahedl, C.}, year={1995} }'
  chicago: Müller, Wolfgang, Georg Lehrenfeld, and C. Tahedl. “Complete Visual Specification
    and Animations of Protocols.” In <i>Proceedings of ASP-DAC’95/CHDL’95/VLSI’95
    with EDA Technofair</i>. Chiba, Japan , 1995. <a href="https://doi.org/10.1109/ASPDAC.1995.486383">https://doi.org/10.1109/ASPDAC.1995.486383</a>.
  ieee: 'W. Müller, G. Lehrenfeld, and C. Tahedl, “Complete Visual Specification and
    Animations of Protocols,” 1995, doi: <a href="https://doi.org/10.1109/ASPDAC.1995.486383">10.1109/ASPDAC.1995.486383</a>.'
  mla: Müller, Wolfgang, et al. “Complete Visual Specification and Animations of Protocols.”
    <i>Proceedings of ASP-DAC’95/CHDL’95/VLSI’95 with EDA Technofair</i>, 1995, doi:<a
    href="https://doi.org/10.1109/ASPDAC.1995.486383">10.1109/ASPDAC.1995.486383</a>.
  short: 'W. Müller, G. Lehrenfeld, C. Tahedl, in: Proceedings of ASP-DAC’95/CHDL’95/VLSI’95
    with EDA Technofair, Chiba, Japan , 1995.'
date_created: 2023-01-24T12:05:55Z
date_updated: 2023-01-24T12:05:59Z
department:
- _id: '672'
doi: 10.1109/ASPDAC.1995.486383
keyword:
- Animation
- Protocols
- Timing
- Computer languages
- Electronic mail
- Context modeling
- Visualization
- Control systems
- Flow graphs
- Trademarks
language:
- iso: eng
place: 'Chiba, Japan '
publication: Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair
publication_identifier:
  isbn:
  - 4-930813-67-0
status: public
title: Complete Visual Specification and Animations of Protocols
type: conference
user_id: '5786'
year: '1995'
...