[{"place":" Niagara Falls, NY, USA ","date_created":"2023-01-17T08:46:14Z","type":"conference","keyword":["Analytical models","Hardware design languages","Microprocessors","Cost function","Data models","Search problems","IP networks"],"department":[{"_id":"672"}],"publication":"Proceedings of SOCC2012","citation":{"apa":"Xie, T., Müller, W., &#38; Letombe, F. (2012). Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. <i>Proceedings of SOCC2012</i>. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>","ieee":"T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor,” 2012, doi: <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","chicago":"Xie, Tao , Wolfgang Müller, and Florian Letombe. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” In <i>Proceedings of SOCC2012</i>.  Niagara Falls, NY, USA : IEEE, 2012. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>.","short":"T. Xie, W. Müller, F. Letombe, in: Proceedings of SOCC2012, IEEE,  Niagara Falls, NY, USA , 2012.","mla":"Xie, Tao, et al. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” <i>Proceedings of SOCC2012</i>, IEEE, 2012, doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","ama":"Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. In: <i>Proceedings of SOCC2012</i>. IEEE; 2012. doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>","bibtex":"@inproceedings{Xie_Müller_Letombe_2012, place={ Niagara Falls, NY, USA }, title={Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}, DOI={<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>}, booktitle={Proceedings of SOCC2012}, publisher={IEEE}, author={Xie, Tao  and Müller, Wolfgang and Letombe, Florian}, year={2012} }"},"abstract":[{"text":"This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP.","lang":"eng"}],"_id":"36994","language":[{"iso":"eng"}],"publisher":"IEEE","doi":"10.1109/SOCC.2012.6398362","user_id":"5786","status":"public","year":"2012","title":"Mutation-Analysis Driven Functional Verification of a Soft Microprocessor","author":[{"full_name":"Xie, Tao ","first_name":"Tao ","last_name":"Xie"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"full_name":"Letombe, Florian","first_name":"Florian","last_name":"Letombe"}],"publication_identifier":{"eisbn":["978-1-4673-1295-0"]},"date_updated":"2023-01-17T08:46:29Z"},{"extern":"1","citation":{"mla":"Müller-Wienbergen, Felix, et al. “Leaving the Beaten Tracks in Creative Work – A Design Theory for Systems That Support Convergent and Divergent Thinking.” <i>Journal of the Association for Information Systems</i>, no. 11, 2011, pp. 714--740, doi:<a href=\"https://doi.org/10.1016/S0006-3495(00)76637-9\">10.1016/S0006-3495(00)76637-9</a>.","bibtex":"@article{Müller-Wienbergen_Müller_Seidel_Becker_2011, title={Leaving the Beaten Tracks in Creative Work – A Design Theory for Systems that Support Convergent and Divergent Thinking}, DOI={<a href=\"https://doi.org/10.1016/S0006-3495(00)76637-9\">10.1016/S0006-3495(00)76637-9</a>}, number={11}, journal={Journal of the Association for Information Systems}, author={Müller-Wienbergen, Felix and Müller, Oliver and Seidel, Stefan and Becker, Jörg}, year={2011}, pages={714--740} }","ama":"Müller-Wienbergen F, Müller O, Seidel S, Becker J. Leaving the Beaten Tracks in Creative Work – A Design Theory for Systems that Support Convergent and Divergent Thinking. <i>Journal of the Association for Information Systems</i>. 2011;(11):714--740. doi:<a href=\"https://doi.org/10.1016/S0006-3495(00)76637-9\">10.1016/S0006-3495(00)76637-9</a>","ieee":"F. Müller-Wienbergen, O. Müller, S. Seidel, and J. Becker, “Leaving the Beaten Tracks in Creative Work – A Design Theory for Systems that Support Convergent and Divergent Thinking,” <i>Journal of the Association for Information Systems</i>, no. 11, pp. 714--740, 2011.","apa":"Müller-Wienbergen, F., Müller, O., Seidel, S., &#38; Becker, J. (2011). Leaving the Beaten Tracks in Creative Work – A Design Theory for Systems that Support Convergent and Divergent Thinking. <i>Journal of the Association for Information Systems</i>, (11), 714--740. <a href=\"https://doi.org/10.1016/S0006-3495(00)76637-9\">https://doi.org/10.1016/S0006-3495(00)76637-9</a>","chicago":"Müller-Wienbergen, Felix, Oliver Müller, Stefan Seidel, and Jörg Becker. “Leaving the Beaten Tracks in Creative Work – A Design Theory for Systems That Support Convergent and Divergent Thinking.” <i>Journal of the Association for Information Systems</i>, no. 11 (2011): 714--740. <a href=\"https://doi.org/10.1016/S0006-3495(00)76637-9\">https://doi.org/10.1016/S0006-3495(00)76637-9</a>.","short":"F. Müller-Wienbergen, O. Müller, S. Seidel, J. Becker, Journal of the Association for Information Systems (2011) 714--740."},"publication":"Journal of the Association for Information Systems","issue":"11","keyword":["Creativity","Creativity Support Systems","convergent thinking","design theory","divergent thinking"],"type":"journal_article","date_created":"2018-10-12T08:37:03Z","date_updated":"2022-01-06T07:01:19Z","publication_identifier":{"issn":["15369323"],"isbn":["1536-9323"]},"author":[{"full_name":"Müller-Wienbergen, Felix","last_name":"Müller-Wienbergen","first_name":"Felix"},{"first_name":"Oliver","last_name":"Müller","full_name":"Müller, Oliver","id":"72849"},{"full_name":"Seidel, Stefan","last_name":"Seidel","first_name":"Stefan"},{"last_name":"Becker","first_name":"Jörg","full_name":"Becker, Jörg"}],"title":"Leaving the Beaten Tracks in Creative Work – A Design Theory for Systems that Support Convergent and Divergent Thinking","year":"2011","status":"public","doi":"10.1016/S0006-3495(00)76637-9","user_id":"72849","_id":"4708","language":[{"iso":"eng"}],"page":"714--740"},{"user_id":"44006","volume":19,"page":"206-219","_id":"11850","status":"public","oa":"1","citation":{"ama":"Krueger A, Warsitz E, Haeb-Umbach R. Speech Enhancement With a GSC-Like Structure Employing Eigenvector-Based Transfer Function Ratios Estimation. <i>IEEE Transactions on Audio, Speech, and Language Processing</i>. 2011;19(1):206-219. doi:<a href=\"https://doi.org/10.1109/TASL.2010.2047324\">10.1109/TASL.2010.2047324</a>","bibtex":"@article{Krueger_Warsitz_Haeb-Umbach_2011, title={Speech Enhancement With a GSC-Like Structure Employing Eigenvector-Based Transfer Function Ratios Estimation}, volume={19}, DOI={<a href=\"https://doi.org/10.1109/TASL.2010.2047324\">10.1109/TASL.2010.2047324</a>}, number={1}, journal={IEEE Transactions on Audio, Speech, and Language Processing}, author={Krueger, Alexander and Warsitz, Ernst and Haeb-Umbach, Reinhold}, year={2011}, pages={206–219} }","mla":"Krueger, Alexander, et al. “Speech Enhancement With a GSC-Like Structure Employing Eigenvector-Based Transfer Function Ratios Estimation.” <i>IEEE Transactions on Audio, Speech, and Language Processing</i>, vol. 19, no. 1, 2011, pp. 206–19, doi:<a href=\"https://doi.org/10.1109/TASL.2010.2047324\">10.1109/TASL.2010.2047324</a>.","chicago":"Krueger, Alexander, Ernst Warsitz, and Reinhold Haeb-Umbach. “Speech Enhancement With a GSC-Like Structure Employing Eigenvector-Based Transfer Function Ratios Estimation.” <i>IEEE Transactions on Audio, Speech, and Language Processing</i> 19, no. 1 (2011): 206–19. <a href=\"https://doi.org/10.1109/TASL.2010.2047324\">https://doi.org/10.1109/TASL.2010.2047324</a>.","short":"A. Krueger, E. Warsitz, R. Haeb-Umbach, IEEE Transactions on Audio, Speech, and Language Processing 19 (2011) 206–219.","apa":"Krueger, A., Warsitz, E., &#38; Haeb-Umbach, R. (2011). Speech Enhancement With a GSC-Like Structure Employing Eigenvector-Based Transfer Function Ratios Estimation. <i>IEEE Transactions on Audio, Speech, and Language Processing</i>, <i>19</i>(1), 206–219. <a href=\"https://doi.org/10.1109/TASL.2010.2047324\">https://doi.org/10.1109/TASL.2010.2047324</a>","ieee":"A. Krueger, E. Warsitz, and R. Haeb-Umbach, “Speech Enhancement With a GSC-Like Structure Employing Eigenvector-Based Transfer Function Ratios Estimation,” <i>IEEE Transactions on Audio, Speech, and Language Processing</i>, vol. 19, no. 1, pp. 206–219, 2011."},"doi":"10.1109/TASL.2010.2047324","main_file_link":[{"open_access":"1","url":"https://groups.uni-paderborn.de/nt/pubs/2011/KrWaHa11.pdf"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:11Z","intvolume":"        19","year":"2011","title":"Speech Enhancement With a GSC-Like Structure Employing Eigenvector-Based Transfer Function Ratios Estimation","author":[{"full_name":"Krueger, Alexander","last_name":"Krueger","first_name":"Alexander"},{"full_name":"Warsitz, Ernst","first_name":"Ernst","last_name":"Warsitz"},{"full_name":"Haeb-Umbach, Reinhold","last_name":"Haeb-Umbach","first_name":"Reinhold","id":"242"}],"keyword":["acoustical transfer function ratio","adaptive eigenvector tracking","array signal processing","beamformer design","blocking matrix","eigenvalues and eigenfunctions","eigenvector-based transfer function ratios estimation","generalized sidelobe canceler","interference reduction","iterative methods","power iteration method","reduced speech distortions","reverberant enclosure","reverberation","speech enhancement","stationary noise"],"type":"journal_article","department":[{"_id":"54"}],"date_created":"2019-07-12T05:29:28Z","abstract":[{"text":"In this paper, we present a novel blocking matrix and fixed beamformer design for a generalized sidelobe canceler for speech enhancement in a reverberant enclosure. They are based on a new method for estimating the acoustical transfer function ratios in the presence of stationary noise. The estimation method relies on solving a generalized eigenvalue problem in each frequency bin. An adaptive eigenvector tracking utilizing the power iteration method is employed and shown to achieve a high convergence speed. Simulation results demonstrate that the proposed beamformer leads to better noise and interference reduction and reduced speech distortions compared to other blocking matrix designs from the literature.","lang":"eng"}],"publication":"IEEE Transactions on Audio, Speech, and Language Processing","issue":"1"},{"citation":{"apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }"},"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","quality_controlled":"1","date_created":"2018-04-03T15:08:13Z","place":"New York, NY, USA","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"type":"conference","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"author":[{"last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Michael","last_name":"Kauschke","full_name":"Kauschke, Michael"}],"status":"public","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","year":"2011","date_updated":"2023-09-26T13:45:04Z","language":[{"iso":"eng"}],"_id":"2200","publisher":"ACM","page":"177-180","user_id":"15278","doi":"10.1145/1950413.1950448"},{"date_updated":"2025-02-26T14:44:15Z","year":"2011","title":"HDL-Mutation Based Simulation Data Generation by Propagation Guided Search","status":"public","publication_identifier":{"isbn":["978-1-4577-1048-3"]},"author":[{"first_name":"Tao","last_name":"Xie","full_name":"Xie, Tao"},{"id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller"},{"full_name":"Letombe, Florian","last_name":"Letombe","first_name":"Florian"}],"user_id":"5786","doi":"10.1109/DSD.2011.83","publisher":"IEEE","_id":"37002","language":[{"iso":"eng"}],"abstract":[{"text":"HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.","lang":"eng"}],"publication":"Proceedings of Euromicro DSD 2011","citation":{"bibtex":"@inproceedings{Xie_Müller_Letombe_2011, place={Oulu, Finnland}, title={HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}, DOI={<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>}, booktitle={Proceedings of Euromicro DSD 2011}, publisher={IEEE}, author={Xie, Tao and Müller, Wolfgang and Letombe, Florian}, year={2011} }","chicago":"Xie, Tao, Wolfgang Müller, and Florian Letombe. “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.” In <i>Proceedings of Euromicro DSD 2011</i>. Oulu, Finnland: IEEE, 2011. <a href=\"https://doi.org/10.1109/DSD.2011.83\">https://doi.org/10.1109/DSD.2011.83</a>.","ama":"Xie T, Müller W, Letombe F. HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. In: <i>Proceedings of Euromicro DSD 2011</i>. IEEE; 2011. doi:<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>","short":"T. Xie, W. Müller, F. Letombe, in: Proceedings of Euromicro DSD 2011, IEEE, Oulu, Finnland, 2011.","ieee":"T. Xie, W. Müller, and F. Letombe, “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search,” 2011, doi: <a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>.","apa":"Xie, T., Müller, W., &#38; Letombe, F. (2011). HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. <i>Proceedings of Euromicro DSD 2011</i>. <a href=\"https://doi.org/10.1109/DSD.2011.83\">https://doi.org/10.1109/DSD.2011.83</a>","mla":"Xie, Tao, et al. “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.” <i>Proceedings of Euromicro DSD 2011</i>, IEEE, 2011, doi:<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>."},"keyword":["Hardware design languages","Cost function","Computational modeling","Fault detection","Data models","Analytical models","Testing"],"type":"conference","department":[{"_id":"672"}],"date_created":"2023-01-17T09:02:48Z","place":"Oulu, Finnland"},{"file_date_updated":"2018-12-13T15:20:13Z","citation":{"bibtex":"@inproceedings{Bodenstein_Schryen_Neumann_2010, title={From “Take-it-or-leave-it” offers to “Take-it-or-be-left-out” Ultimatum - A trade mechanism for Online Services}, booktitle={18th European Conference on Information Systems (ECIS 2010)}, author={Bodenstein, Christian and Schryen, Guido and Neumann, Dirk}, year={2010} }","ama":"Bodenstein C, Schryen G, Neumann D. From “Take-it-or-leave-it” offers to “Take-it-or-be-left-out” Ultimatum - A trade mechanism for Online Services. In: <i>18th European Conference on Information Systems (ECIS 2010)</i>. ; 2010.","mla":"Bodenstein, Christian, et al. “From ‘Take-It-or-Leave-It’ Offers to ‘Take-It-or-Be-Left-out’ Ultimatum - A Trade Mechanism for Online Services.” <i>18th European Conference on Information Systems (ECIS 2010)</i>, 2010.","chicago":"Bodenstein, Christian, Guido Schryen, and Dirk Neumann. “From ‘Take-It-or-Leave-It’ Offers to ‘Take-It-or-Be-Left-out’ Ultimatum - A Trade Mechanism for Online Services.” In <i>18th European Conference on Information Systems (ECIS 2010)</i>, 2010.","short":"C. Bodenstein, G. Schryen, D. Neumann, in: 18th European Conference on Information Systems (ECIS 2010), 2010.","ieee":"C. Bodenstein, G. Schryen, and D. Neumann, “From ‘Take-it-or-leave-it’ offers to ‘Take-it-or-be-left-out’ Ultimatum - A trade mechanism for Online Services,” in <i>18th European Conference on Information Systems (ECIS 2010)</i>, 2010.","apa":"Bodenstein, C., Schryen, G., &#38; Neumann, D. (2010). From “Take-it-or-leave-it” offers to “Take-it-or-be-left-out” Ultimatum - A trade mechanism for Online Services. In <i>18th European Conference on Information Systems (ECIS 2010)</i>."},"oa":"1","status":"public","has_accepted_license":"1","_id":"5690","ddc":["000"],"user_id":"61579","publication":"18th European Conference on Information Systems (ECIS 2010)","abstract":[{"text":"In a world, where more and more businesses seem to trade in an online market, the supply of online services to supply the ever-growing demand could quickly reach its capacity limits. Online service providers may find themselves maxed out at peak operation levels during high-traffic timeslots but too little demand during low-traffic timeslots, although the latter is becoming less frequent. At this point not only deciding which user is allocated what level of service becomes essential, but also the magnitude of the service provided, can be controlled by pricing. Pricing is an important factor when efficient and acceptable allocation of resources between individuals must be reached. Without prices, transferring or sharing goods would be impossible. In sharing information, pricing a product however is not as simple as relatively pricing an apple or a pear. Often the costs, and hence the prices are simply unknown. Backed by this scenario, the online services market could be combined with the market design mechanism of diamonds. For this we propose an ultimatum pricing strategy which effectively allows for valuations to be accounted for, but no longer a necessity when pricing in grid, cloud or other online computing environments.","lang":"eng"}],"extern":"1","file":[{"date_created":"2018-12-11T15:22:41Z","creator":"hsiemes","file_id":"6191","content_type":"application/pdf","file_name":"Take it or leave it - ECIS - Proof.pdf","file_size":247621,"access_level":"open_access","relation":"main_file","date_updated":"2018-12-13T15:20:13Z"}],"date_created":"2018-11-14T15:48:39Z","type":"conference","keyword":["Posted Price","Ultimatum Game","Energy Efficiency","Mechanism Design"],"department":[{"_id":"277"}],"title":"From \"Take-it-or-leave-it\" offers to \"Take-it-or-be-left-out\" Ultimatum - A trade mechanism for Online Services","year":"2010","author":[{"full_name":"Bodenstein, Christian","last_name":"Bodenstein","first_name":"Christian"},{"first_name":"Guido","last_name":"Schryen","full_name":"Schryen, Guido","id":"72850"},{"full_name":"Neumann, Dirk","last_name":"Neumann","first_name":"Dirk"}],"date_updated":"2022-01-06T07:02:34Z","language":[{"iso":"eng"}]},{"doi":"10.1109/INDIN.2010.5549490","user_id":"55222","page":"739 -744","language":[{"iso":"eng"}],"_id":"9760","date_updated":"2022-01-06T07:04:19Z","year":"2010","title":"Guideline for the dependability-oriented design of self-optimizing systems","status":"public","author":[{"last_name":"Sondermann-Wölke","first_name":"Christoph","full_name":"Sondermann-Wölke, Christoph"},{"id":"210","first_name":"Tobias","last_name":"Hemsel","full_name":"Hemsel, Tobias"},{"first_name":"Walter","last_name":"Sextro","full_name":"Sextro, Walter","id":"21220"},{"full_name":"Gausemeier, Jürgen","first_name":"Jürgen","last_name":"Gausemeier"},{"first_name":"Sebastian","last_name":"Pook","full_name":"Pook, Sebastian"}],"keyword":["RailCab","dependability-critical behavior","dependability-oriented design","failure mode","rail-bound vehicle","secure self-optimizing systems","self-optimizing function modules","optimisation","railways","self-adjusting systems"],"type":"conference","department":[{"_id":"151"}],"date_created":"2019-05-13T10:25:26Z","quality_controlled":"1","abstract":[{"text":"Self-optimizing systems are able to adapt their behavior autonomously according to their current self-determined objectives. Unforeseen influences could lead to dependability-critical behavior of the system. Methods are required which secure self-optimizing systems during operation. These methods to increase the dependability of the system should already be taken into consideration in the design process. This paper presents a guideline for the dependability-oriented design of self-optimizing systems, which integrates established classical methods like failure mode and effects analysis as well as methods based on self-optimization. On the one hand self-optimization is used to increase the dependability of the system by integrating objectives like safety, availability, and reliability to the objectives of the system. On the other hand methods are required to ensure the self-optimization itself. As basis for this guideline serves the principle solution of the system. The six phases of the guideline extend the design process and lead to an enhanced principle solution. Additionally, the guideline illustrates phases to implement and validate the self-optimizing system. The proposed guideline is applied to an innovative rail-bound vehicle, called RailCab, which is equipped with self-optimizing function modules.","lang":"eng"}],"publication":"Industrial Informatics (INDIN), 2010 8th IEEE International Conference on","citation":{"chicago":"Sondermann-Wölke, Christoph, Tobias Hemsel, Walter Sextro, Jürgen Gausemeier, and Sebastian Pook. “Guideline for the Dependability-Oriented Design of Self-Optimizing Systems.” In <i>Industrial Informatics (INDIN), 2010 8th IEEE International Conference On</i>, 739–44, 2010. <a href=\"https://doi.org/10.1109/INDIN.2010.5549490\">https://doi.org/10.1109/INDIN.2010.5549490</a>.","short":"C. Sondermann-Wölke, T. Hemsel, W. Sextro, J. Gausemeier, S. Pook, in: Industrial Informatics (INDIN), 2010 8th IEEE International Conference On, 2010, pp. 739–744.","apa":"Sondermann-Wölke, C., Hemsel, T., Sextro, W., Gausemeier, J., &#38; Pook, S. (2010). Guideline for the dependability-oriented design of self-optimizing systems. In <i>Industrial Informatics (INDIN), 2010 8th IEEE International Conference on</i> (pp. 739–744). <a href=\"https://doi.org/10.1109/INDIN.2010.5549490\">https://doi.org/10.1109/INDIN.2010.5549490</a>","ieee":"C. Sondermann-Wölke, T. Hemsel, W. Sextro, J. Gausemeier, and S. Pook, “Guideline for the dependability-oriented design of self-optimizing systems,” in <i>Industrial Informatics (INDIN), 2010 8th IEEE International Conference on</i>, 2010, pp. 739–744.","ama":"Sondermann-Wölke C, Hemsel T, Sextro W, Gausemeier J, Pook S. Guideline for the dependability-oriented design of self-optimizing systems. In: <i>Industrial Informatics (INDIN), 2010 8th IEEE International Conference On</i>. ; 2010:739-744. doi:<a href=\"https://doi.org/10.1109/INDIN.2010.5549490\">10.1109/INDIN.2010.5549490</a>","bibtex":"@inproceedings{Sondermann-Wölke_Hemsel_Sextro_Gausemeier_Pook_2010, title={Guideline for the dependability-oriented design of self-optimizing systems}, DOI={<a href=\"https://doi.org/10.1109/INDIN.2010.5549490\">10.1109/INDIN.2010.5549490</a>}, booktitle={Industrial Informatics (INDIN), 2010 8th IEEE International Conference on}, author={Sondermann-Wölke, Christoph and Hemsel, Tobias and Sextro, Walter and Gausemeier, Jürgen and Pook, Sebastian}, year={2010}, pages={739–744} }","mla":"Sondermann-Wölke, Christoph, et al. “Guideline for the Dependability-Oriented Design of Self-Optimizing Systems.” <i>Industrial Informatics (INDIN), 2010 8th IEEE International Conference On</i>, 2010, pp. 739–44, doi:<a href=\"https://doi.org/10.1109/INDIN.2010.5549490\">10.1109/INDIN.2010.5549490</a>."}},{"publication_identifier":{"issn":["1755-5817"]},"author":[{"first_name":"Y.T.","last_name":"Azene","full_name":"Azene, Y.T."},{"first_name":"R.","last_name":"Roy","full_name":"Roy, R."},{"full_name":"Farrugia, D.","first_name":"D.","last_name":"Farrugia"},{"full_name":"Onisa, C.","last_name":"Onisa","first_name":"C."},{"full_name":"Mehnen, J.","first_name":"J.","last_name":"Mehnen"},{"full_name":"Trautmann, Heike","orcid":"0000-0002-9788-8282","first_name":"Heike","last_name":"Trautmann","id":"100740"}],"title":"Work roll cooling system design optimisation in presence of uncertainty and constrains","year":"2010","intvolume":"         2","date_updated":"2023-10-16T13:57:23Z","language":[{"iso":"eng"}],"doi":"https://doi.org/10.1016/j.cirpj.2010.06.001","publication":"CIRP Journal of Manufacturing Science and Technology","issue":"4","abstract":[{"lang":"eng","text":"The paper presents a framework to optimise the design of work roll based on the cooling performance. The framework develops meta-models from a set of finite element analyses (FEA) of the roll cooling. A design of experiment technique is used to identify the FEA runs. The research also identifies sources of uncertainties in the design process. A robust evolutionary multi-objective evaluation technique is applied to the design optimisation in constrained problems with real life uncertainty. The approach handles uncertainties associated both with design variables and fitness functions. Constraints violation within the neighbourhood of a design is considered as part of a measurement for degree of feasibility and robustness of a solution."}],"date_created":"2023-08-04T16:09:19Z","department":[{"_id":"34"},{"_id":"819"}],"type":"journal_article","keyword":["Roll cooling design","Uncertainty","Design optimisation","Multi-objective optimisation","Constraint in design"],"status":"public","_id":"46411","page":"290-298","volume":2,"user_id":"15504","citation":{"bibtex":"@article{Azene_Roy_Farrugia_Onisa_Mehnen_Trautmann_2010, title={Work roll cooling system design optimisation in presence of uncertainty and constrains}, volume={2}, DOI={<a href=\"https://doi.org/10.1016/j.cirpj.2010.06.001\">https://doi.org/10.1016/j.cirpj.2010.06.001</a>}, number={4}, journal={CIRP Journal of Manufacturing Science and Technology}, author={Azene, Y.T. and Roy, R. and Farrugia, D. and Onisa, C. and Mehnen, J. and Trautmann, Heike}, year={2010}, pages={290–298} }","chicago":"Azene, Y.T., R. Roy, D. Farrugia, C. Onisa, J. Mehnen, and Heike Trautmann. “Work Roll Cooling System Design Optimisation in Presence of Uncertainty and Constrains.” <i>CIRP Journal of Manufacturing Science and Technology</i> 2, no. 4 (2010): 290–98. <a href=\"https://doi.org/10.1016/j.cirpj.2010.06.001\">https://doi.org/10.1016/j.cirpj.2010.06.001</a>.","ama":"Azene YT, Roy R, Farrugia D, Onisa C, Mehnen J, Trautmann H. Work roll cooling system design optimisation in presence of uncertainty and constrains. <i>CIRP Journal of Manufacturing Science and Technology</i>. 2010;2(4):290-298. doi:<a href=\"https://doi.org/10.1016/j.cirpj.2010.06.001\">https://doi.org/10.1016/j.cirpj.2010.06.001</a>","short":"Y.T. Azene, R. Roy, D. Farrugia, C. Onisa, J. Mehnen, H. Trautmann, CIRP Journal of Manufacturing Science and Technology 2 (2010) 290–298.","ieee":"Y. T. Azene, R. Roy, D. Farrugia, C. Onisa, J. Mehnen, and H. Trautmann, “Work roll cooling system design optimisation in presence of uncertainty and constrains,” <i>CIRP Journal of Manufacturing Science and Technology</i>, vol. 2, no. 4, pp. 290–298, 2010, doi: <a href=\"https://doi.org/10.1016/j.cirpj.2010.06.001\">https://doi.org/10.1016/j.cirpj.2010.06.001</a>.","apa":"Azene, Y. T., Roy, R., Farrugia, D., Onisa, C., Mehnen, J., &#38; Trautmann, H. (2010). Work roll cooling system design optimisation in presence of uncertainty and constrains. <i>CIRP Journal of Manufacturing Science and Technology</i>, <i>2</i>(4), 290–298. <a href=\"https://doi.org/10.1016/j.cirpj.2010.06.001\">https://doi.org/10.1016/j.cirpj.2010.06.001</a>","mla":"Azene, Y. T., et al. “Work Roll Cooling System Design Optimisation in Presence of Uncertainty and Constrains.” <i>CIRP Journal of Manufacturing Science and Technology</i>, vol. 2, no. 4, 2010, pp. 290–98, doi:<a href=\"https://doi.org/10.1016/j.cirpj.2010.06.001\">https://doi.org/10.1016/j.cirpj.2010.06.001</a>."}},{"date_updated":"2023-01-17T10:47:37Z","year":"2010","status":"public","title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","author":[{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"},{"full_name":"Di Guglielmo, Giuseppe","last_name":"Di Guglielmo","first_name":"Giuseppe"},{"last_name":"Fummi","first_name":"Franco","full_name":"Fummi, Franco"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"last_name":"Pravadelli","first_name":"Graziano","full_name":"Pravadelli, Graziano"},{"last_name":"Xie","first_name":"Tao","full_name":"Xie, Tao"}],"publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"conference":{"location":"Dresden","name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"user_id":"5786","doi":"10.1109/DATE.2010.5456965","_id":"37040","publisher":"IEEE","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms."}],"publication":"Proceedings of DATE’10","citation":{"mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }","apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010."},"keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"type":"conference","department":[{"_id":"672"}],"date_created":"2023-01-17T10:47:29Z","place":"Dresden"},{"citation":{"mla":"Becker, Markus, et al. <i>A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_15\">10.1007/978-3-642-15234-4_15</a>.","apa":"Becker, M., Zabel, H., &#38; Müller, W. (2010). <i>A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_15\">https://doi.org/10.1007/978-3-642-15234-4_15</a>","ieee":"M. Becker, H. Zabel, and W. Müller, “A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement,” 2010, doi: <a href=\"https://doi.org/10.1007/978-3-642-15234-4_15\">10.1007/978-3-642-15234-4_15</a>.","short":"M. Becker, H. Zabel, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.","ama":"Becker M, Zabel H, Müller W. A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_15\">10.1007/978-3-642-15234-4_15</a>","chicago":"Becker, Markus, Henning Zabel, and Wolfgang Müller. “A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_15\">https://doi.org/10.1007/978-3-642-15234-4_15</a>.","bibtex":"@inproceedings{Becker_Zabel_Müller_2010, place={Dordrecht}, title={A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-15234-4_15\">10.1007/978-3-642-15234-4_15</a>}, publisher={Springer Verlag}, author={Becker, Markus and Zabel, Henning and Müller, Wolfgang}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }"},"abstract":[{"lang":"eng","text":"In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, we combine the native speed of an abstract real-time operating system (RTOS) model in SystemC with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU. In order to support stepwise RTOS software refinement from system level to the target software, each task can be separately migrated between the native execution and the ISS. By adapting the dynamic binary translation approach to an efficient but yet very accurate synchronization scheme the overhead of QEMU user mode execution is only factor two compared to native SystemC. Furthermore, the simulation speed increases almost linearly according to the utilization of the task set abstracted by the native execution. Hereby, the simulation time can be considerably reduced by cosimulating just a subset of tasks on QEMU."}],"place":"Dordrecht","date_created":"2023-01-17T11:01:30Z","keyword":["Application Programming Interface     User Mode     Kernel Space     System Level Design     Mixed Level"],"type":"conference","department":[{"_id":"672"}],"status":"public","year":"2010","title":"A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement","conference":{"name":"IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2010)"},"publication_identifier":{"isbn":["978-3-642-15233-7"]},"author":[{"full_name":"Becker, Markus","first_name":"Markus","last_name":"Becker"},{"last_name":"Zabel","first_name":"Henning","full_name":"Zabel, Henning"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"}],"date_updated":"2023-01-17T11:03:00Z","_id":"37046","language":[{"iso":"eng"}],"publisher":"Springer Verlag","doi":"10.1007/978-3-642-15234-4_15","user_id":"5786","editor":[{"first_name":"L.","last_name":"Kleinjohann","full_name":"Kleinjohann, L."},{"full_name":"Kleinjohann, B.","first_name":"B.","last_name":"Kleinjohann"}]},{"keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"type":"conference","date_created":"2023-01-17T10:44:46Z","place":"Dresden","abstract":[{"text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.","lang":"eng"}],"publication":"Proceedings of DATE’10","citation":{"bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }","ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>.","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>"},"user_id":"5786","doi":"10.1109/DATE.2010.5456965","publisher":"IEEE","_id":"37039","language":[{"iso":"eng"}],"date_updated":"2025-03-12T16:39:17Z","year":"2010","status":"public","title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","author":[{"last_name":"Becker","first_name":"Markus","full_name":"Becker, Markus"},{"first_name":"Giuseppe","last_name":"Di Guglielmo","full_name":"Di Guglielmo, Giuseppe"},{"full_name":"Fummi, Franco","last_name":"Fummi","first_name":"Franco"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"first_name":"Graziano","last_name":"Pravadelli","full_name":"Pravadelli, Graziano"},{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"}],"publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"}},{"main_file_link":[{"open_access":"1","url":"http://idl.iscram.org/files/pottebaum/2010/847_Pottebaum_etal2010.pdf"}],"_id":"24065","language":[{"iso":"eng"}],"user_id":"405","editor":[{"first_name":"Simon","last_name":"French","full_name":"French, Simon"},{"first_name":"Brian","last_name":"Tomaszewski","full_name":"Tomaszewski, Brian"},{"first_name":"Chris","last_name":"Zobel","full_name":"Zobel, Chris"}],"year":"2010","status":"public","title":"Design and modeling of a domain ontology for fire protection","author":[{"id":"405","orcid":"http://orcid.org/0000-0001-8778-2989","first_name":"Jens","last_name":"Pottebaum","full_name":"Pottebaum, Jens"},{"full_name":"Japs, Anna Maria","first_name":"Anna Maria","last_name":"Japs"},{"full_name":"Prödel, Stephan","first_name":"Stephan","last_name":"Prödel"},{"last_name":"Koch","first_name":"Rainer","full_name":"Koch, Rainer"}],"date_updated":"2026-03-31T03:52:00Z","place":"Seattle, WA","date_created":"2021-09-09T12:27:14Z","keyword":["Command and control process","Command and control systems","Design and modeling","Domain ontologies","Emergency response","Fire extinguishers","Fire protection","Heterogeneous domains","Information analysis","Information sharing","Information systems","Interoperability","Ontology language","Semantic technologies","Semantic Web","Semantics"],"type":"conference","oa":"1","publication":"ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management","citation":{"ama":"Pottebaum J, Japs AM, Prödel S, Koch R. Design and modeling of a domain ontology for fire protection. In: French S, Tomaszewski B, Zobel C, eds. <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>. ; 2010.","bibtex":"@inproceedings{Pottebaum_Japs_Prödel_Koch_2010, place={Seattle, WA}, title={Design and modeling of a domain ontology for fire protection}, booktitle={ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management}, author={Pottebaum, Jens and Japs, Anna Maria and Prödel, Stephan and Koch, Rainer}, editor={French, Simon and Tomaszewski, Brian and Zobel, Chris}, year={2010} }","mla":"Pottebaum, Jens, et al. “Design and Modeling of a Domain Ontology for Fire Protection.” <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>, edited by Simon French et al., 2010.","chicago":"Pottebaum, Jens, Anna Maria Japs, Stephan Prödel, and Rainer Koch. “Design and Modeling of a Domain Ontology for Fire Protection.” In <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>, edited by Simon French, Brian Tomaszewski, and Chris Zobel. Seattle, WA, 2010.","short":"J. Pottebaum, A.M. Japs, S. Prödel, R. Koch, in: S. French, B. Tomaszewski, C. Zobel (Eds.), ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management, Seattle, WA, 2010.","apa":"Pottebaum, J., Japs, A. M., Prödel, S., &#38; Koch, R. (2010). Design and modeling of a domain ontology for fire protection. In S. French, B. Tomaszewski, &#38; C. Zobel (Eds.), <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>.","ieee":"J. Pottebaum, A. M. Japs, S. Prödel, and R. Koch, “Design and modeling of a domain ontology for fire protection,” in <i>ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management</i>, 2010."},"quality_controlled":"1"},{"author":[{"full_name":"Vanderperren, Yves","last_name":"Vanderperren","first_name":"Yves"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"full_name":"Dahaene, Wim","last_name":"Dahaene","first_name":"Wim"}],"title":"UML for Electronic Systems Design – A Comprehensive Overview","status":"public","year":"2008","intvolume":"        12","date_updated":"2022-12-19T12:23:56Z","publisher":"Springer-Verlag","_id":"34563","language":[{"iso":"eng"}],"page":"261-292","volume":12,"doi":"10.1007/s10617-008-9028-9","user_id":"5786","citation":{"short":"Y. Vanderperren, W. Müller, W. Dahaene, Design Automation for Embedded Systems 12 (2008) 261–292.","chicago":"Vanderperren, Yves, Wolfgang Müller, and Wim Dahaene. “UML for Electronic Systems Design – A Comprehensive Overview.” <i>Design Automation for Embedded Systems</i> 12 (2008): 261–92. <a href=\"https://doi.org/10.1007/s10617-008-9028-9\">https://doi.org/10.1007/s10617-008-9028-9</a>.","apa":"Vanderperren, Y., Müller, W., &#38; Dahaene, W. (2008). UML for Electronic Systems Design – A Comprehensive Overview. <i>Design Automation for Embedded Systems</i>, <i>12</i>, 261–292. <a href=\"https://doi.org/10.1007/s10617-008-9028-9\">https://doi.org/10.1007/s10617-008-9028-9</a>","ieee":"Y. Vanderperren, W. Müller, and W. Dahaene, “UML for Electronic Systems Design – A Comprehensive Overview,” <i>Design Automation for Embedded Systems</i>, vol. 12, pp. 261–292, 2008, doi: <a href=\"https://doi.org/10.1007/s10617-008-9028-9\">10.1007/s10617-008-9028-9</a>.","ama":"Vanderperren Y, Müller W, Dahaene W. UML for Electronic Systems Design – A Comprehensive Overview. <i>Design Automation for Embedded Systems</i>. 2008;12:261-292. doi:<a href=\"https://doi.org/10.1007/s10617-008-9028-9\">10.1007/s10617-008-9028-9</a>","bibtex":"@article{Vanderperren_Müller_Dahaene_2008, title={UML for Electronic Systems Design – A Comprehensive Overview}, volume={12}, DOI={<a href=\"https://doi.org/10.1007/s10617-008-9028-9\">10.1007/s10617-008-9028-9</a>}, journal={Design Automation for Embedded Systems}, publisher={Springer-Verlag}, author={Vanderperren, Yves and Müller, Wolfgang and Dahaene, Wim}, year={2008}, pages={261–292} }","mla":"Vanderperren, Yves, et al. “UML for Electronic Systems Design – A Comprehensive Overview.” <i>Design Automation for Embedded Systems</i>, vol. 12, Springer-Verlag, 2008, pp. 261–92, doi:<a href=\"https://doi.org/10.1007/s10617-008-9028-9\">10.1007/s10617-008-9028-9</a>."},"publication":"Design Automation for Embedded Systems","abstract":[{"text":"UML has been widely accepted by the software community for several years. As electronic systems design can no longer be seen as an isolated hardware design activity, UML becomes of significant interest as a unification language for systems description combining both HW and SW components. This article provides a comprehensive view of the UML applied to System-on-Chip (SoC) and hardware-related embedded systems design. The modeling concepts in the UML language are first introduced, including major diagrams for the representation of the behavior and the structure of systems. The principles behind application specific UML customizations (UML profiles) are summarized, and several examples relevant for SoC design are given, such as the SysML (System Modeling Language) and the SoC Profile. Thereafter, various approaches associating UML with existing HW/SW design languages are presented. Beyond language aspects, the article addresses the question of UML-based design flows, and shows how UML can be applied concretely to the development of electronic-based systems. The current situation about tool support constitutes the last focus of the article. In particular, we show how UML tools can be combined with well-known simulation environments, such as MATLAB.","lang":"eng"}],"date_created":"2022-12-19T12:18:21Z","department":[{"_id":"672"}],"keyword":["UML     SysML     Model-based design     System specification     Modelling languages"],"type":"journal_article"},{"doi":"10.1007/s12193-008-0003-3","language":[{"iso":"eng"}],"intvolume":"         2","date_updated":"2022-12-19T12:23:05Z","author":[{"full_name":"Schäfer, Robbie","last_name":"Schäfer","first_name":"Robbie"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"year":"2008","title":"Assessment of a Multimodal Interaction and Rendering System against Established Design Principles","department":[{"_id":"672"}],"type":"journal_article","keyword":["Interaction architecture     Abstract interaction objects     Dialogue model     Transformations     Multimodality     Multi-device     Design principles"],"date_created":"2022-12-19T12:22:50Z","abstract":[{"text":"To provide user interfaces for a rich set of devices and interaction modalities, we follow a model-based development methodology. We devised an architecture which deploys user interfaces specified as dialogue models with abstract interaction objects and allows context-based adaptations by means of an external transcoding process. For the validation of the applicability of this methodology for developing usable multimodal multi-device systems, we present two case studies based on proof-of-concept implementations and assessed them with a large set of established design principles and different types of modality cooperation.","lang":"eng"}],"issue":"1","publication":"Journal on Multimodal User Interfaces","volume":2,"user_id":"5786","publisher":"Springer-Verlag","_id":"34564","page":"25-41","status":"public","citation":{"bibtex":"@article{Schäfer_Müller_2008, title={Assessment of a Multimodal Interaction and Rendering System against Established Design Principles}, volume={2}, DOI={<a href=\"https://doi.org/10.1007/s12193-008-0003-3\">10.1007/s12193-008-0003-3</a>}, number={1}, journal={Journal on Multimodal User Interfaces}, publisher={Springer-Verlag}, author={Schäfer, Robbie and Müller, Wolfgang}, year={2008}, pages={25–41} }","ama":"Schäfer R, Müller W. Assessment of a Multimodal Interaction and Rendering System against Established Design Principles. <i>Journal on Multimodal User Interfaces</i>. 2008;2(1):25-41. doi:<a href=\"https://doi.org/10.1007/s12193-008-0003-3\">10.1007/s12193-008-0003-3</a>","mla":"Schäfer, Robbie, and Wolfgang Müller. “Assessment of a Multimodal Interaction and Rendering System against Established Design Principles.” <i>Journal on Multimodal User Interfaces</i>, vol. 2, no. 1, Springer-Verlag, 2008, pp. 25–41, doi:<a href=\"https://doi.org/10.1007/s12193-008-0003-3\">10.1007/s12193-008-0003-3</a>.","chicago":"Schäfer, Robbie, and Wolfgang Müller. “Assessment of a Multimodal Interaction and Rendering System against Established Design Principles.” <i>Journal on Multimodal User Interfaces</i> 2, no. 1 (2008): 25–41. <a href=\"https://doi.org/10.1007/s12193-008-0003-3\">https://doi.org/10.1007/s12193-008-0003-3</a>.","short":"R. Schäfer, W. Müller, Journal on Multimodal User Interfaces 2 (2008) 25–41.","ieee":"R. Schäfer and W. Müller, “Assessment of a Multimodal Interaction and Rendering System against Established Design Principles,” <i>Journal on Multimodal User Interfaces</i>, vol. 2, no. 1, pp. 25–41, 2008, doi: <a href=\"https://doi.org/10.1007/s12193-008-0003-3\">10.1007/s12193-008-0003-3</a>.","apa":"Schäfer, R., &#38; Müller, W. (2008). Assessment of a Multimodal Interaction and Rendering System against Established Design Principles. <i>Journal on Multimodal User Interfaces</i>, <i>2</i>(1), 25–41. <a href=\"https://doi.org/10.1007/s12193-008-0003-3\">https://doi.org/10.1007/s12193-008-0003-3</a>"}},{"language":[{"iso":"eng"}],"author":[{"first_name":"Guido","last_name":"Schryen","full_name":"Schryen, Guido","id":"72850"}],"year":"2007","title":"The Impact that Placing Email Addresses on the Internet has on the Receipt of Spam ? An Empirical Analysis","intvolume":"         2","date_updated":"2022-01-06T07:02:22Z","date_created":"2018-11-14T14:53:12Z","file":[{"date_created":"2018-12-18T13:27:01Z","creator":"hsiemes","content_type":"application/pdf","file_id":"6326","date_updated":"2018-12-18T13:27:01Z","relation":"main_file","file_size":3026200,"access_level":"open_access","file_name":"The Impact that Placing Email Addresses on the Internet has on the Receipt of Spam - An Empirical Analysis - Journal version.pdf"}],"department":[{"_id":"277"}],"type":"journal_article","keyword":["Address-obfuscating techniques","email","empirical analysis","honeypot","security by design","security by obscurity","spam"],"publication":"Computers & Security","issue":"5","extern":"1","abstract":[{"lang":"eng","text":"Email communication is encumbered with a mass of email messages which their recipients have neither requested nor require. Even worse, the impacts of these messages are far from being simply an annoyance, as they also involve economic damage. This manuscript examines the resource ?email addresses?, which is vital for any potential bulk mailer and spammer. Both a methodology and a honeypot conceptualization for implementing an empirical analysis of the usage of email addresses placed on the Internet are proposed here. Their objective is to assess, on a quantitative basis, the extent of the current harassment and its development over time. This ?framework? is intended to be extensible to measuring the effectiveness of address-obscuring techniques. The implementation of a pilot honeypot is described, which led to key findings, some of them being: (1) Web placements attract more than two-thirds (70\\%) of all honeypot spam emails, followed by newsgroup placements (28.6\\%) and newsletter subscriptions (1.4\\%), (2) the proportions of spam relating to the email addresses? top-level domain can be statistically assumed to be uniformly distributed, (3) More than 43\\% of addresses on the web have been abused, whereas about 27\\% was the case for addresses on newsgroups and only about 4\\% was the case for addresses used for a newsletter subscription, (4) Regarding the development of email addresses? attractiveness for spammers over time, the service ?web sites? features a negative linear relationship, whereas the service ?Usenet? hows a negative exponential relationship. (5) Only 1.54\\% of the spam emails showed an interrelation between the topic of the spam email and that of the location where the recipient?s address was placed, so that spammers are assumed to send their emails in a ?context insensitive? manner. The results of the empirical analysis motivate the need for the protection of email addresses through obscuration. We analyze this need by formulating requirements for address obscuring techniques and we reveal to which extent today?s most relevant approaches fulfill these requirements."}],"publisher":"Elsevier","_id":"5658","page":"361-372","volume":2,"user_id":"61579","ddc":["000"],"status":"public","has_accepted_license":"1","oa":"1","citation":{"ama":"Schryen G. The Impact that Placing Email Addresses on the Internet has on the Receipt of Spam ? An Empirical Analysis. <i>Computers &#38; Security</i>. 2007;2(5):361-372.","bibtex":"@article{Schryen_2007, title={The Impact that Placing Email Addresses on the Internet has on the Receipt of Spam ? An Empirical Analysis}, volume={2}, number={5}, journal={Computers &#38; Security}, publisher={Elsevier}, author={Schryen, Guido}, year={2007}, pages={361–372} }","mla":"Schryen, Guido. “The Impact That Placing Email Addresses on the Internet Has on the Receipt of Spam ? An Empirical Analysis.” <i>Computers &#38; Security</i>, vol. 2, no. 5, Elsevier, 2007, pp. 361–72.","short":"G. Schryen, Computers &#38; Security 2 (2007) 361–372.","chicago":"Schryen, Guido. “The Impact That Placing Email Addresses on the Internet Has on the Receipt of Spam ? An Empirical Analysis.” <i>Computers &#38; Security</i> 2, no. 5 (2007): 361–72.","apa":"Schryen, G. (2007). The Impact that Placing Email Addresses on the Internet has on the Receipt of Spam ? An Empirical Analysis. <i>Computers &#38; Security</i>, <i>2</i>(5), 361–372.","ieee":"G. Schryen, “The Impact that Placing Email Addresses on the Internet has on the Receipt of Spam ? An Empirical Analysis,” <i>Computers &#38; Security</i>, vol. 2, no. 5, pp. 361–372, 2007."},"file_date_updated":"2018-12-18T13:27:01Z"},{"citation":{"short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.","chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, 447–54. IEEE, 2007. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>.","apa":"Kaufmann, P., &#38; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i> (pp. 447–454). Edinburgh, UK: IEEE. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>","ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, Edinburgh, UK, 2007, pp. 447–454.","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>. IEEE; 2007:447-454. doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }","mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, IEEE, 2007, pp. 447–54, doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>."},"page":"447-454","_id":"6508","publisher":"IEEE","user_id":"3118","status":"public","conference":{"end_date":"2007-08-08","name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","start_date":"2007-08-05","location":"Edinburgh, UK"},"date_created":"2019-01-08T09:52:43Z","keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"type":"conference","department":[{"_id":"78"}],"publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","abstract":[{"text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/ahs.2007.73","year":"2007","title":"MOVES: A Modular Framework for Hardware Evolution","author":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"publication_identifier":{"isbn":["076952866X","9780769528663"]},"publication_status":"published","date_updated":"2022-01-06T07:03:08Z"},{"quality_controlled":"1","abstract":[{"text":"This paper presents a general model based on the electromechanical circuit theory. The model is set up as a mechanical equivalent model for base excited systems and describes the behaviour of a piezoelectric element around one resonance frequency which is sufficient for most practical applications. The model is extended to obtain the influence of geometrical and material properties. The derivated properties are used to describe the parameters of the general model which is easy to handle. Using this model either the calculation of the output power on a specific electric load or the determination of the design of the used piezoelectric element for a needed electric output power is possible. The paper focuses on the design of the ratio of length and width of a piezoelectric bimorph. The validity of the model is shown by the comparison of computed and experimental results.","lang":"eng"}],"publication":"ASME 2006 International Mechanical Engineering Congress and Exposition","citation":{"ama":"Richter B, Twiefel J, Hemsel T, Wallaschek J. Model based design of piezoelectric generators utilizing geometrical and material properties. In: <i>ASME 2006 International Mechanical Engineering Congress and Exposition</i>. Chicago, Illinois, USA; 2006. doi:<a href=\"https://doi.org/doi:10.1115/IMECE2006-14862\">doi:10.1115/IMECE2006-14862</a>","bibtex":"@inproceedings{Richter_Twiefel_Hemsel_Wallaschek_2006, place={Chicago, Illinois, USA}, title={Model based design of piezoelectric generators utilizing geometrical and material properties}, DOI={<a href=\"https://doi.org/doi:10.1115/IMECE2006-14862\">doi:10.1115/IMECE2006-14862</a>}, booktitle={ASME 2006 International Mechanical Engineering Congress and Exposition}, author={Richter, Björn and Twiefel, Jens and Hemsel, Tobias and Wallaschek, Jörg}, year={2006} }","mla":"Richter, Björn, et al. “Model Based Design of Piezoelectric Generators Utilizing Geometrical and Material Properties.” <i>ASME 2006 International Mechanical Engineering Congress and Exposition</i>, 2006, doi:<a href=\"https://doi.org/doi:10.1115/IMECE2006-14862\">doi:10.1115/IMECE2006-14862</a>.","chicago":"Richter, Björn, Jens Twiefel, Tobias Hemsel, and Jörg Wallaschek. “Model Based Design of Piezoelectric Generators Utilizing Geometrical and Material Properties.” In <i>ASME 2006 International Mechanical Engineering Congress and Exposition</i>. Chicago, Illinois, USA, 2006. <a href=\"https://doi.org/doi:10.1115/IMECE2006-14862\">https://doi.org/doi:10.1115/IMECE2006-14862</a>.","short":"B. Richter, J. Twiefel, T. Hemsel, J. Wallaschek, in: ASME 2006 International Mechanical Engineering Congress and Exposition, Chicago, Illinois, USA, 2006.","apa":"Richter, B., Twiefel, J., Hemsel, T., &#38; Wallaschek, J. (2006). Model based design of piezoelectric generators utilizing geometrical and material properties. In <i>ASME 2006 International Mechanical Engineering Congress and Exposition</i>. Chicago, Illinois, USA. <a href=\"https://doi.org/doi:10.1115/IMECE2006-14862\">https://doi.org/doi:10.1115/IMECE2006-14862</a>","ieee":"B. Richter, J. Twiefel, T. Hemsel, and J. Wallaschek, “Model based design of piezoelectric generators utilizing geometrical and material properties,” in <i>ASME 2006 International Mechanical Engineering Congress and Exposition</i>, 2006."},"type":"conference","keyword":["Materials properties","Design","Generators"],"department":[{"_id":"151"}],"date_created":"2019-04-29T09:37:45Z","place":"Chicago, Illinois, USA","date_updated":"2022-01-06T07:04:16Z","title":"Model based design of piezoelectric generators utilizing geometrical and material properties","year":"2006","status":"public","author":[{"full_name":"Richter, Björn","last_name":"Richter","first_name":"Björn"},{"first_name":"Jens","last_name":"Twiefel","full_name":"Twiefel, Jens"},{"full_name":"Hemsel, Tobias","last_name":"Hemsel","first_name":"Tobias","id":"210"},{"first_name":"Jörg","last_name":"Wallaschek","full_name":"Wallaschek, Jörg"}],"user_id":"55222","doi":"doi:10.1115/IMECE2006-14862","language":[{"iso":"eng"}],"_id":"9548"},{"abstract":[{"text":"TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML.","lang":"eng"}],"citation":{"chicago":"Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.” In <i>Proc. of ISOLA 06</i>. Paphos, Cyprus, 2006. <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">https://doi.org/10.1109/ISoLA.2006.37</a>.","short":"J. Großmann, W. Müller, in: Proc. of ISOLA 06, Paphos, Cyprus, 2006.","ieee":"J. Großmann and W. Müller, “A Formal Behavioral Semantics for TestML,” Paphos, Cyprus, 2006, doi: <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>.","apa":"Großmann, J., &#38; Müller, W. (2006). A Formal Behavioral Semantics for TestML. <i>Proc. of ISOLA 06</i>. <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">https://doi.org/10.1109/ISoLA.2006.37</a>","bibtex":"@inproceedings{Großmann_Müller_2006, place={Paphos, Cyprus}, title={A Formal Behavioral Semantics for TestML}, DOI={<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>}, booktitle={Proc. of ISOLA 06}, author={Großmann, Jürgen and Müller, Wolfgang}, year={2006} }","ama":"Großmann J, Müller W. A Formal Behavioral Semantics for TestML. In: <i>Proc. of ISOLA 06</i>. ; 2006. doi:<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>","mla":"Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.” <i>Proc. of ISOLA 06</i>, 2006, doi:<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>."},"publication":"Proc. of ISOLA 06","department":[{"_id":"672"}],"keyword":["System testing","Software testing","Automotive engineering","Automatic testing","Machinery production industries","Protocols","Hardware design languages","Samarium","XML","Computer industry"],"type":"conference","date_created":"2023-01-23T12:00:06Z","place":"Paphos, Cyprus","date_updated":"2023-01-23T12:06:26Z","author":[{"full_name":"Großmann, Jürgen","first_name":"Jürgen","last_name":"Großmann"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}],"publication_identifier":{"isbn":["978-0-7695-3071-0"]},"conference":{"location":"Paphos, Cyprus"},"title":"A Formal Behavioral Semantics for TestML","status":"public","year":"2006","user_id":"5786","doi":"10.1109/ISoLA.2006.37","_id":"38107","language":[{"iso":"eng"}]},{"user_id":"5786","_id":"39030","language":[{"iso":"eng"}],"date_updated":"2023-01-24T08:12:26Z","author":[{"first_name":"Tim","last_name":"Schattkowsky","full_name":"Schattkowsky, Tim"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}],"year":"2005","title":"A UML Virtual Machine for Embedded Systems","status":"public","department":[{"_id":"672"}],"type":"conference","keyword":["UML","Executable Models","Hardware/Software Co-design","Virtual Machine","Embedded Systems"],"date_created":"2023-01-24T08:12:20Z","place":"Las Vegas, NV","abstract":[{"lang":"eng","text":"StateCharts are well accepted for embedded systems\r\nspecification for various applications. However, for the\r\nspecification of complex systems they have several\r\nlimitations. In this article, we present a novel approach to\r\nefficiently execute an UML 2.0 subset for embedded real-\r\ntime systems implementation with focus on hardware\r\ninterrupts, software exceptions, and timeouts. We\r\nintroduce a UML Virtual Machine, which directly\r\nexecutes sequence diagrams, which are embedded into\r\nhierarchically structured state transition diagrams.\r\nWhereas state diagrams are directly executed as\r\nEmbedded State Machines (ESMs), sequence diagrams\r\nare translated into UVM Bytecode. The final UVM\r\nexecution is performed by the interaction of the ESM and\r\nthe Bytecode Interpreter. Due to our completely model-\r\nbased approach, the UVM runtime kernel is easily\r\nadaptable and scalable to different scheduling and\r\nmemory management strategies."}],"citation":{"bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Las Vegas, NV}, title={A UML Virtual Machine for Embedded Systems}, booktitle={Proceedings of ISNG 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }","ama":"Schattkowsky T, Müller W. A UML Virtual Machine for Embedded Systems. In: <i>Proceedings of ISNG 05</i>. ; 2005.","mla":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” <i>Proceedings of ISNG 05</i>, 2005.","short":"T. Schattkowsky, W. Müller, in: Proceedings of ISNG 05, Las Vegas, NV, 2005.","chicago":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” In <i>Proceedings of ISNG 05</i>. Las Vegas, NV, 2005.","ieee":"T. Schattkowsky and W. Müller, “A UML Virtual Machine for Embedded Systems,” 2005.","apa":"Schattkowsky, T., &#38; Müller, W. (2005). A UML Virtual Machine for Embedded Systems. <i>Proceedings of ISNG 05</i>."},"publication":"Proceedings of ISNG 05"},{"abstract":[{"text":"Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.","lang":"eng"}],"citation":{"apa":"Schattkowsky, T., &#38; Müller, W. (2005). Transformation of UML State Machines for Direct Execution. <i>Proceedings of VL/HCC 05</i>. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>","ieee":"T. Schattkowsky and W. Müller, “Transformation of UML State Machines for Direct Execution,” 2005, doi: <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","chicago":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” In <i>Proceedings of VL/HCC 05</i>. Dallas, TX, USA, 2005. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>.","short":"T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA, 2005.","mla":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” <i>Proceedings of VL/HCC 05</i>, 2005, doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","ama":"Schattkowsky T, Müller W. Transformation of UML State Machines for Direct Execution. In: <i>Proceedings of VL/HCC 05</i>. ; 2005. doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Dallas, TX, USA}, title={Transformation of UML State Machines for Direct Execution}, DOI={<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>}, booktitle={Proceedings of VL/HCC 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }"},"publication":"Proceedings of VL/HCC 05","department":[{"_id":"672"}],"keyword":["Unified modeling language","Software design","Virtual machining","Embedded system","Programming","Documentation","Hardware","Computer languages","Operating systems","Runtime"],"type":"conference","place":"Dallas, TX, USA","date_created":"2023-01-24T08:18:10Z","date_updated":"2023-01-24T08:18:27Z","author":[{"first_name":"Tim","last_name":"Schattkowsky","full_name":"Schattkowsky, Tim"},{"last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243"}],"publication_identifier":{"isbn":["0-7695-2443-5"]},"status":"public","year":"2005","title":"Transformation of UML State Machines for Direct Execution","doi":"10.1109/VLHCC.2005.64","user_id":"5786","language":[{"iso":"eng"}],"_id":"39032"}]