@inproceedings{56166,
  abstract     = {{Developing Intelligent Technical Systems (ITS) involves a complex process encompassing planning, analysis, design, production, and maintenance. Model-Based Systems Engineering (MBSE) is a key methodology for systematic systems engineering. Designing models for ITS requires harmonious interaction of various elements, posing a challenge in MBSE. Leveraging Generative Artificial Intelligence, we generated a dataset for modeling, using prompt engineering on large language models. The generated artifacts can aid engineers in MBSE design or serve as synthetic training data for AI assistants.}},
  author       = {{Kulkarni, Pranav Jayant and Tissen, Denis and Bernijazov, Ruslan and Dumitrescu, Roman}},
  booktitle    = {{DS 130: Proceedings of NordDesign 2024}},
  editor       = {{Malmqvist, J. and Candi, M. and Saemundsson, R. and Bystrom, F. and Isaksson, O.}},
  keywords     = {{Data Driven Design, Design Automation, Systems Engineering (SE), Artificial Intelligence (AI)}},
  location     = {{Reykjavik}},
  pages        = {{617--625}},
  title        = {{{Towards Automated Design: Automatically Generating Modeling Elements with Prompt Engineering and Generative Artificial Intelligence}}},
  doi          = {{10.35199/NORDDESIGN2024.66}},
  year         = {{2024}},
}

@inproceedings{10577,
  abstract     = {{State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution.

In this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing.}},
  author       = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}},
  booktitle    = {{Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI '19}},
  isbn         = {{9781450362528}},
  keywords     = {{Approximate computing, design automation, parameter selection, circuit synthesis}},
  location     = {{Tysons Corner, VA, USA}},
  publisher    = {{ACM}},
  title        = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}},
  doi          = {{10.1145/3299874.3317998}},
  year         = {{2019}},
}

@inproceedings{39061,
  abstract     = {{This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML state diagrams, which are translated to the formal B language and are model checked for real-time properties. By means of the B language and a B theorem prover, refined state diagrams are verified against their abstract representation. The approach is presented by means of the refinement of a digital echo cancellation unit.}},
  author       = {{Krupp, Alexander and Müller, Wolfgang and Oliver, Ian}},
  booktitle    = {{Proceedings of DATE’04 Designers' Forum}},
  isbn         = {{0-7695-2085-5}},
  keywords     = {{Echo cancellers, Logic, Unified modeling language, Automata, Data structures, Boolean functions, Electronic design automation and methodology, Prototypes, Specification languages, Constraint theory}},
  title        = {{{Formal Refinement and Model Checking of An Echo Cancellation Unit}}},
  doi          = {{10.1109/DATE.2004.1269214}},
  year         = {{2004}},
}

@inproceedings{39421,
  abstract     = {{We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.}},
  author       = {{Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W. and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}},
  booktitle    = {{Proceedings of the Design, Automation, and Test in Europe (DATE’01)}},
  isbn         = {{0-7695-0993-2}},
  keywords     = {{Yarn, Formal verification, Kernel, Hardware design languages, Electronic design automation and methodology, Algebra, Computational modeling, Logic functions, Computer languages, Clocks}},
  publisher    = {{IEEE}},
  title        = {{{The Simulation Semantics of SystemC}}},
  doi          = {{10.1109/DATE.2001.915002}},
  year         = {{2001}},
}