---
_id: '56166'
abstract:
- lang: eng
  text: Developing Intelligent Technical Systems (ITS) involves a complex process
    encompassing planning, analysis, design, production, and maintenance. Model-Based
    Systems Engineering (MBSE) is a key methodology for systematic systems engineering.
    Designing models for ITS requires harmonious interaction of various elements,
    posing a challenge in MBSE. Leveraging Generative Artificial Intelligence, we
    generated a dataset for modeling, using prompt engineering on large language models.
    The generated artifacts can aid engineers in MBSE design or serve as synthetic
    training data for AI assistants.
author:
- first_name: Pranav Jayant
  full_name: Kulkarni, Pranav Jayant
  id: '86782'
  last_name: Kulkarni
- first_name: Denis
  full_name: Tissen, Denis
  id: '44458'
  last_name: Tissen
- first_name: Ruslan
  full_name: Bernijazov, Ruslan
  id: '36312'
  last_name: Bernijazov
- first_name: Roman
  full_name: Dumitrescu, Roman
  id: '16190'
  last_name: Dumitrescu
citation:
  ama: 'Kulkarni PJ, Tissen D, Bernijazov R, Dumitrescu R. Towards Automated Design:
    Automatically Generating Modeling Elements with Prompt Engineering and Generative
    Artificial Intelligence. In: Malmqvist J, Candi M, Saemundsson R, Bystrom F, Isaksson
    O, eds. <i>DS 130: Proceedings of NordDesign 2024</i>. ; 2024:617-625. doi:<a
    href="https://doi.org/10.35199/NORDDESIGN2024.66">10.35199/NORDDESIGN2024.66</a>'
  apa: 'Kulkarni, P. J., Tissen, D., Bernijazov, R., &#38; Dumitrescu, R. (2024).
    Towards Automated Design: Automatically Generating Modeling Elements with Prompt
    Engineering and Generative Artificial Intelligence. In J. Malmqvist, M. Candi,
    R. Saemundsson, F. Bystrom, &#38; O. Isaksson (Eds.), <i>DS 130: Proceedings of
    NordDesign 2024</i> (pp. 617–625). <a href="https://doi.org/10.35199/NORDDESIGN2024.66">https://doi.org/10.35199/NORDDESIGN2024.66</a>'
  bibtex: '@inproceedings{Kulkarni_Tissen_Bernijazov_Dumitrescu_2024, title={Towards
    Automated Design: Automatically Generating Modeling Elements with Prompt Engineering
    and Generative Artificial Intelligence}, DOI={<a href="https://doi.org/10.35199/NORDDESIGN2024.66">10.35199/NORDDESIGN2024.66</a>},
    booktitle={DS 130: Proceedings of NordDesign 2024}, author={Kulkarni, Pranav Jayant
    and Tissen, Denis and Bernijazov, Ruslan and Dumitrescu, Roman}, editor={Malmqvist,
    J. and Candi, M. and Saemundsson, R. and Bystrom, F. and Isaksson, O.}, year={2024},
    pages={617–625} }'
  chicago: 'Kulkarni, Pranav Jayant, Denis Tissen, Ruslan Bernijazov, and Roman Dumitrescu.
    “Towards Automated Design: Automatically Generating Modeling Elements with Prompt
    Engineering and Generative Artificial Intelligence.” In <i>DS 130: Proceedings
    of NordDesign 2024</i>, edited by J. Malmqvist, M. Candi, R. Saemundsson, F. Bystrom,
    and O. Isaksson, 617–25, 2024. <a href="https://doi.org/10.35199/NORDDESIGN2024.66">https://doi.org/10.35199/NORDDESIGN2024.66</a>.'
  ieee: 'P. J. Kulkarni, D. Tissen, R. Bernijazov, and R. Dumitrescu, “Towards Automated
    Design: Automatically Generating Modeling Elements with Prompt Engineering and
    Generative Artificial Intelligence,” in <i>DS 130: Proceedings of NordDesign 2024</i>,
    Reykjavik, 2024, pp. 617–625, doi: <a href="https://doi.org/10.35199/NORDDESIGN2024.66">10.35199/NORDDESIGN2024.66</a>.'
  mla: 'Kulkarni, Pranav Jayant, et al. “Towards Automated Design: Automatically Generating
    Modeling Elements with Prompt Engineering and Generative Artificial Intelligence.”
    <i>DS 130: Proceedings of NordDesign 2024</i>, edited by J. Malmqvist et al.,
    2024, pp. 617–25, doi:<a href="https://doi.org/10.35199/NORDDESIGN2024.66">10.35199/NORDDESIGN2024.66</a>.'
  short: 'P.J. Kulkarni, D. Tissen, R. Bernijazov, R. Dumitrescu, in: J. Malmqvist,
    M. Candi, R. Saemundsson, F. Bystrom, O. Isaksson (Eds.), DS 130: Proceedings
    of NordDesign 2024, 2024, pp. 617–625.'
conference:
  end_date: 2024-08-14
  location: Reykjavik
  name: NordDesign Conference 2024
  start_date: 2024-08-12
date_created: 2024-09-17T09:56:43Z
date_updated: 2024-09-17T09:57:07Z
doi: 10.35199/NORDDESIGN2024.66
editor:
- first_name: J.
  full_name: Malmqvist, J.
  last_name: Malmqvist
- first_name: M.
  full_name: Candi, M.
  last_name: Candi
- first_name: R.
  full_name: Saemundsson, R.
  last_name: Saemundsson
- first_name: F.
  full_name: Bystrom, F.
  last_name: Bystrom
- first_name: O.
  full_name: Isaksson, O.
  last_name: Isaksson
keyword:
- Data Driven Design
- Design Automation
- Systems Engineering (SE)
- Artificial Intelligence (AI)
language:
- iso: eng
page: 617-625
publication: 'DS 130: Proceedings of NordDesign 2024'
publication_identifier:
  unknown:
  - 978-1-912254-21-7
publication_status: epub_ahead
related_material:
  link:
  - relation: confirmation
    url: https://www.designsociety.org/publication/47658/Towards+Automated+Design%3A+Automatically+Generating+Modeling+Elements+with+Prompt+Engineering+and+Generative+Artificial+Intelligence
status: public
title: 'Towards Automated Design: Automatically Generating Modeling Elements with
  Prompt Engineering and Generative Artificial Intelligence'
type: conference
user_id: '86782'
year: '2024'
...
---
_id: '10577'
abstract:
- lang: eng
  text: "State-of-the-art frameworks for generating approximate circuits automatically
    explore the search space in an iterative process - often greedily. Synthesis and
    verification processes are invoked in each iteration to evaluate the found solutions
    and to guide the search algorithm. As a result, a large number of approximate
    circuits is subjected to analysis - leading to long runtimes - but only a few
    approximate circuits might form an acceptable solution.\r\n\r\nIn this paper,
    we present our Jump Search (JS) method which seeks to reduce the runtime of an
    approximation process by reducing the number of expensive synthesis and verification
    steps. To reduce the runtime, JS computes impact factors for each approximation
    candidate in the circuit to create a selection of approximate circuits without
    invoking synthesis or verification processes. We denote the selection as path
    from which JS determines the final solution. In our experimental results, JS achieved
    speed-ups of up to 57x while area savings remain comparable to the reference search
    method, Simulated Annealing."
author:
- first_name: Linus Matthias
  full_name: Witschen, Linus Matthias
  id: '49051'
  last_name: Witschen
- first_name: Hassan
  full_name: Ghasemzadeh Mohammadi, Hassan
  id: '61186'
  last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
  full_name: Artmann, Matthias
  last_name: Artmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
    A Fast Technique for the Synthesis of Approximate Circuits. In: <i>Proceedings
    of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19</i>. New York, NY,
    USA: ACM; 2019. doi:<a href="https://doi.org/10.1145/3299874.3317998">10.1145/3299874.3317998</a>'
  apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., &#38; Platzner, M.
    (2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
    In <i>Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19</i>.
    New York, NY, USA: ACM. <a href="https://doi.org/10.1145/3299874.3317998">https://doi.org/10.1145/3299874.3317998</a>'
  bibtex: '@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New
    York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate
    Circuits}, DOI={<a href="https://doi.org/10.1145/3299874.3317998">10.1145/3299874.3317998</a>},
    booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI
    ’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi,
    Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }'
  chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
    and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
    Circuits.” In <i>Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI
    ’19</i>. New York, NY, USA: ACM, 2019. <a href="https://doi.org/10.1145/3299874.3317998">https://doi.org/10.1145/3299874.3317998</a>.'
  ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
    Search: A Fast Technique for the Synthesis of Approximate Circuits,” in <i>Proceedings
    of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19</i>, Tysons Corner,
    VA, USA, 2019.'
  mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
    of Approximate Circuits.” <i>Proceedings of the 2019 on Great Lakes Symposium
    on VLSI  - GLSVLSI ’19</i>, ACM, 2019, doi:<a href="https://doi.org/10.1145/3299874.3317998">10.1145/3299874.3317998</a>.'
  short: 'L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings
    of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, ACM, New York, NY,
    USA, 2019.'
conference:
  end_date: 2019-05-11
  location: Tysons Corner, VA, USA
  name: ACM Great Lakes Symposium on VLSI (GLSVLSI)
  start_date: 2019-05-09
date_created: 2019-07-08T15:13:10Z
date_updated: 2022-01-06T06:50:45Z
department:
- _id: '78'
doi: 10.1145/3299874.3317998
keyword:
- Approximate computing
- design automation
- parameter selection
- circuit synthesis
language:
- iso: eng
place: New York, NY, USA
project:
- _id: '52'
  name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI '19
publication_identifier:
  isbn:
  - '9781450362528'
publication_status: published
publisher: ACM
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: conference
user_id: '49051'
year: '2019'
...
---
_id: '39061'
abstract:
- lang: eng
  text: This article presents an approach, which combines theorem proving-based refinement
    with model checking for state based real-time systems. Our verification flow starts
    from UML state diagrams, which are translated to the formal B language and are
    model checked for real-time properties. By means of the B language and a B theorem
    prover, refined state diagrams are verified against their abstract representation.
    The approach is presented by means of the refinement of a digital echo cancellation
    unit.
author:
- first_name: Alexander
  full_name: Krupp, Alexander
  last_name: Krupp
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Ian
  full_name: Oliver, Ian
  last_name: Oliver
citation:
  ama: 'Krupp A, Müller W, Oliver I. Formal Refinement and Model Checking of An Echo
    Cancellation Unit. In: <i>Proceedings of DATE’04 Designers’ Forum</i>. ; 2004.
    doi:<a href="https://doi.org/10.1109/DATE.2004.1269214">10.1109/DATE.2004.1269214</a>'
  apa: Krupp, A., Müller, W., &#38; Oliver, I. (2004). Formal Refinement and Model
    Checking of An Echo Cancellation Unit. <i>Proceedings of DATE’04 Designers’ Forum</i>.
    Proceedings Design, Automation and Test in Europe Conference and Exhibition. <a
    href="https://doi.org/10.1109/DATE.2004.1269214">https://doi.org/10.1109/DATE.2004.1269214</a>
  bibtex: '@inproceedings{Krupp_Müller_Oliver_2004, place={Paris}, title={Formal Refinement
    and Model Checking of An Echo Cancellation Unit}, DOI={<a href="https://doi.org/10.1109/DATE.2004.1269214">10.1109/DATE.2004.1269214</a>},
    booktitle={Proceedings of DATE’04 Designers’ Forum}, author={Krupp, Alexander
    and Müller, Wolfgang and Oliver, Ian}, year={2004} }'
  chicago: Krupp, Alexander, Wolfgang Müller, and Ian Oliver. “Formal Refinement and
    Model Checking of An Echo Cancellation Unit.” In <i>Proceedings of DATE’04 Designers’
    Forum</i>. Paris, 2004. <a href="https://doi.org/10.1109/DATE.2004.1269214">https://doi.org/10.1109/DATE.2004.1269214</a>.
  ieee: 'A. Krupp, W. Müller, and I. Oliver, “Formal Refinement and Model Checking
    of An Echo Cancellation Unit,” presented at the Proceedings Design, Automation
    and Test in Europe Conference and Exhibition, 2004, doi: <a href="https://doi.org/10.1109/DATE.2004.1269214">10.1109/DATE.2004.1269214</a>.'
  mla: Krupp, Alexander, et al. “Formal Refinement and Model Checking of An Echo Cancellation
    Unit.” <i>Proceedings of DATE’04 Designers’ Forum</i>, 2004, doi:<a href="https://doi.org/10.1109/DATE.2004.1269214">10.1109/DATE.2004.1269214</a>.
  short: 'A. Krupp, W. Müller, I. Oliver, in: Proceedings of DATE’04 Designers’ Forum,
    Paris, 2004.'
conference:
  name: Proceedings Design, Automation and Test in Europe Conference and Exhibition
date_created: 2023-01-24T08:53:26Z
date_updated: 2023-01-24T08:53:31Z
department:
- _id: '672'
doi: 10.1109/DATE.2004.1269214
keyword:
- Echo cancellers
- Logic
- Unified modeling language
- Automata
- Data structures
- Boolean functions
- Electronic design automation and methodology
- Prototypes
- Specification languages
- Constraint theory
language:
- iso: eng
place: Paris
publication: Proceedings of DATE’04 Designers' Forum
publication_identifier:
  isbn:
  - 0-7695-2085-5
status: public
title: Formal Refinement and Model Checking of An Echo Cancellation Unit
type: conference
user_id: '5786'
year: '2004'
...
---
_id: '39421'
abstract:
- lang: eng
  text: We present a rigorous but transparent semantics definition of SystemC that
    covers method, thread, and clocked thread behavior as well as their interaction
    with the simulation kernel process. The semantics includes watching statements,
    signal assignment, and wait statements as they are introduced in SystemC V1.O.
    We present our definition in form of distributed Abstract State Machines (ASMs)
    rules reflecting the view given in the SystemC User's Manual and the reference
    implementation. We mainly see our formal semantics as a concise, unambiguous,
    high-level specification for SystemC-based implementations and for standardization.
    Additionally, it can be used as a sound basis to investigate SystemC interoperability
    with Verilog and VHDL.
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Jürgen
  full_name: Ruf, Jürgen
  last_name: Ruf
- first_name: D. W.
  full_name: Hoffmann, D. W.
  last_name: Hoffmann
- first_name: Joachim
  full_name: Gerlach, Joachim
  last_name: Gerlach
- first_name: Thomas
  full_name: Kropf, Thomas
  last_name: Kropf
- first_name: W.
  full_name: Rosenstiehl, W.
  last_name: Rosenstiehl
citation:
  ama: 'Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation
    Semantics of SystemC. In: <i>Proceedings of the Design, Automation, and Test in
    Europe (DATE’01)</i>. IEEE; 2001. doi:<a href="https://doi.org/10.1109/DATE.2001.915002">10.1109/DATE.2001.915002</a>'
  apa: Müller, W., Ruf, J., Hoffmann, D. W., Gerlach, J., Kropf, T., &#38; Rosenstiehl,
    W. (2001). The Simulation Semantics of SystemC. <i>Proceedings of the Design,
    Automation, and Test in Europe (DATE’01)</i>.  Proceedings Design, Automation
    and Test in Europe. Conference and Exhibition 2001. <a href="https://doi.org/10.1109/DATE.2001.915002">https://doi.org/10.1109/DATE.2001.915002</a>
  bibtex: '@inproceedings{Müller_Ruf_Hoffmann_Gerlach_Kropf_Rosenstiehl_2001, place={Munich,
    Germany }, title={The Simulation Semantics of SystemC}, DOI={<a href="https://doi.org/10.1109/DATE.2001.915002">10.1109/DATE.2001.915002</a>},
    booktitle={Proceedings of the Design, Automation, and Test in Europe (DATE’01)},
    publisher={IEEE}, author={Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W.
    and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}, year={2001} }'
  chicago: 'Müller, Wolfgang, Jürgen Ruf, D. W. Hoffmann, Joachim Gerlach, Thomas
    Kropf, and W. Rosenstiehl. “The Simulation Semantics of SystemC.” In <i>Proceedings
    of the Design, Automation, and Test in Europe (DATE’01)</i>. Munich, Germany :
    IEEE, 2001. <a href="https://doi.org/10.1109/DATE.2001.915002">https://doi.org/10.1109/DATE.2001.915002</a>.'
  ieee: 'W. Müller, J. Ruf, D. W. Hoffmann, J. Gerlach, T. Kropf, and W. Rosenstiehl,
    “The Simulation Semantics of SystemC,” presented at the  Proceedings Design, Automation
    and Test in Europe. Conference and Exhibition 2001, 2001, doi: <a href="https://doi.org/10.1109/DATE.2001.915002">10.1109/DATE.2001.915002</a>.'
  mla: Müller, Wolfgang, et al. “The Simulation Semantics of SystemC.” <i>Proceedings
    of the Design, Automation, and Test in Europe (DATE’01)</i>, IEEE, 2001, doi:<a
    href="https://doi.org/10.1109/DATE.2001.915002">10.1109/DATE.2001.915002</a>.
  short: 'W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl,
    in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE,
    Munich, Germany , 2001.'
conference:
  name: ' Proceedings Design, Automation and Test in Europe. Conference and Exhibition
    2001'
date_created: 2023-01-24T10:39:33Z
date_updated: 2023-01-24T10:39:38Z
department:
- _id: '672'
doi: 10.1109/DATE.2001.915002
keyword:
- Yarn
- Formal verification
- Kernel
- Hardware design languages
- Electronic design automation and methodology
- Algebra
- Computational modeling
- Logic functions
- Computer languages
- Clocks
language:
- iso: eng
place: 'Munich, Germany '
publication: Proceedings of the Design, Automation, and Test in Europe (DATE’01)
publication_identifier:
  isbn:
  - 0-7695-0993-2
publisher: IEEE
status: public
title: The Simulation Semantics of SystemC
type: conference
user_id: '5786'
year: '2001'
...