[{"abstract":[{"text":"UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.","lang":"eng"}],"citation":{"bibtex":"@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian and He, Da and Müller, Wolfgang}, year={2010} }","chicago":"Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>.","short":"F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","ama":"Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>","ieee":"F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>.","apa":"Mischkalla, F., He, D., &#38; Müller, W. (2010). Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>","mla":"Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>."},"publication":"Proceedings of DATE’10","department":[{"_id":"672"}],"type":"conference","keyword":["Unified modeling language","Field programmable gate arrays","Bridges","Helium","Real time systems","Operating systems","Documentation","Application software","XML","Space exploration"],"date_created":"2023-01-17T09:12:35Z","place":"Dresden","date_updated":"2023-01-17T09:12:44Z","publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"author":[{"full_name":"Mischkalla, Fabian","last_name":"Mischkalla","first_name":"Fabian"},{"last_name":"He","first_name":"Da","full_name":"He, Da"},{"full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang","id":"16243"}],"conference":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"},"year":"2010","status":"public","title":"Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems","user_id":"5786","doi":"10.1109/DATE.2010.5456990","_id":"37007","language":[{"iso":"eng"}],"publisher":"IEEE"},{"user_id":"5786","doi":"10.1109/DATE.2005.20","publisher":"IEEE","_id":"39029","language":[{"iso":"eng"}],"date_updated":"2023-01-24T08:10:44Z","author":[{"full_name":"Schattkowsky, Tim","first_name":"Tim","last_name":"Schattkowsky"},{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"},{"first_name":"Achim","last_name":"Rettberg","full_name":"Rettberg, Achim"}],"publication_identifier":{"isbn":["0-7695-2288-2"]},"status":"public","year":"2005","title":"A Model-Based Approach for Executable Specification on Reconfigurable Hardware","department":[{"_id":"672"}],"keyword":["Hardware","Unified modeling language","Virtual machining","Object oriented modeling","Field programmable gate arrays","Java","Microcontrollers","Embedded software","Real time systems","Documentation"],"type":"conference","date_created":"2023-01-24T08:10:40Z","place":"Munich, Germany ","abstract":[{"lang":"eng","text":"UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller."}],"citation":{"mla":"Schattkowsky, Tim, et al. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” <i>Proceedings of DATE’05</i>, IEEE, 2005, doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>.","ama":"Schattkowsky T, Müller W, Rettberg A. A Model-Based Approach for Executable Specification on Reconfigurable Hardware. In: <i>Proceedings of DATE’05</i>. IEEE; 2005. doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>","bibtex":"@inproceedings{Schattkowsky_Müller_Rettberg_2005, place={Munich, Germany }, title={A Model-Based Approach for Executable Specification on Reconfigurable Hardware}, DOI={<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>}, booktitle={Proceedings of DATE’05}, publisher={IEEE}, author={Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}, year={2005} }","apa":"Schattkowsky, T., Müller, W., &#38; Rettberg, A. (2005). A Model-Based Approach for Executable Specification on Reconfigurable Hardware. <i>Proceedings of DATE’05</i>. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>","ieee":"T. Schattkowsky, W. Müller, and A. Rettberg, “A Model-Based Approach for Executable Specification on Reconfigurable Hardware,” 2005, doi: <a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>.","short":"T. Schattkowsky, W. Müller, A. Rettberg, in: Proceedings of DATE’05, IEEE, Munich, Germany , 2005.","chicago":"Schattkowsky, Tim, Wolfgang Müller, and Achim Rettberg. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” In <i>Proceedings of DATE’05</i>. Munich, Germany : IEEE, 2005. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>."},"publication":"Proceedings of DATE’05"},{"place":"Dallas, TX, USA","date_created":"2023-01-24T08:18:10Z","department":[{"_id":"672"}],"type":"conference","keyword":["Unified modeling language","Software design","Virtual machining","Embedded system","Programming","Documentation","Hardware","Computer languages","Operating systems","Runtime"],"citation":{"chicago":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” In <i>Proceedings of VL/HCC 05</i>. Dallas, TX, USA, 2005. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>.","short":"T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA, 2005.","ieee":"T. Schattkowsky and W. Müller, “Transformation of UML State Machines for Direct Execution,” 2005, doi: <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","apa":"Schattkowsky, T., &#38; Müller, W. (2005). Transformation of UML State Machines for Direct Execution. <i>Proceedings of VL/HCC 05</i>. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Dallas, TX, USA}, title={Transformation of UML State Machines for Direct Execution}, DOI={<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>}, booktitle={Proceedings of VL/HCC 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }","ama":"Schattkowsky T, Müller W. Transformation of UML State Machines for Direct Execution. In: <i>Proceedings of VL/HCC 05</i>. ; 2005. doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>","mla":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” <i>Proceedings of VL/HCC 05</i>, 2005, doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>."},"publication":"Proceedings of VL/HCC 05","abstract":[{"lang":"eng","text":"Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution."}],"language":[{"iso":"eng"}],"_id":"39032","doi":"10.1109/VLHCC.2005.64","user_id":"5786","author":[{"full_name":"Schattkowsky, Tim","last_name":"Schattkowsky","first_name":"Tim"},{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"}],"publication_identifier":{"isbn":["0-7695-2443-5"]},"year":"2005","title":"Transformation of UML State Machines for Direct Execution","status":"public","date_updated":"2023-01-24T08:18:27Z"},{"date_created":"2023-01-24T10:10:24Z","place":"Nagoya, Japan","department":[{"_id":"672"}],"keyword":["Standardization","Kernel","Permission","Formal verification","Logic functions","Documentation","Reasoning about programs","Specification languages","Formal specifications","Software systems"],"type":"conference","citation":{"ama":"Müller W, Dömer R, Gerstlauer A. The Formal Execution Semantics of SpecC. In: <i>Proceedings of the ISSS02</i>. ; 2002. doi:<a href=\"https://doi.org/10.1145/581199.581234 \">10.1145/581199.581234 </a>","bibtex":"@inproceedings{Müller_Dömer_Gerstlauer_2002, place={Nagoya, Japan}, title={The Formal Execution Semantics of SpecC}, DOI={<a href=\"https://doi.org/10.1145/581199.581234 \">10.1145/581199.581234 </a>}, booktitle={Proceedings of the ISSS02}, author={Müller, Wolfgang and Dömer, Rainer and Gerstlauer, Andreas}, year={2002} }","mla":"Müller, Wolfgang, et al. “The Formal Execution Semantics of SpecC.” <i>Proceedings of the ISSS02</i>, 2002, doi:<a href=\"https://doi.org/10.1145/581199.581234 \">10.1145/581199.581234 </a>.","chicago":"Müller, Wolfgang, Rainer Dömer, and Andreas Gerstlauer. “The Formal Execution Semantics of SpecC.” In <i>Proceedings of the ISSS02</i>. Nagoya, Japan, 2002. <a href=\"https://doi.org/10.1145/581199.581234 \">https://doi.org/10.1145/581199.581234 </a>.","short":"W. Müller, R. Dömer, A. Gerstlauer, in: Proceedings of the ISSS02, Nagoya, Japan, 2002.","apa":"Müller, W., Dömer, R., &#38; Gerstlauer, A. (2002). The Formal Execution Semantics of SpecC. <i>Proceedings of the ISSS02</i>. <a href=\"https://doi.org/10.1145/581199.581234 \">https://doi.org/10.1145/581199.581234 </a>","ieee":"W. Müller, R. Dömer, and A. Gerstlauer, “The Formal Execution Semantics of SpecC,” 2002, doi: <a href=\"https://doi.org/10.1145/581199.581234 \">10.1145/581199.581234 </a>."},"publication":"Proceedings of the ISSS02","abstract":[{"lang":"eng","text":"We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, wait for, par, and try statements as they are introduced in SpecC. We present our definition in form of distributed abstract state machine (ASM) rules strictly following the lines of the SpecC Language Reference Manual. We mainly see our formal semantics in three application areas. First, it is a concise, unambiguous description for documentation and standardization. Second, it applies as a high-level, pseudo code-oriented specification for the implementation of a SpecC simulator. Finally, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets."}],"_id":"39382","language":[{"iso":"eng"}],"user_id":"5786","doi":"10.1145/581199.581234 ","author":[{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"},{"first_name":"Rainer","last_name":"Dömer","full_name":"Dömer, Rainer"},{"last_name":"Gerstlauer","first_name":"Andreas","full_name":"Gerstlauer, Andreas"}],"publication_identifier":{"isbn":["1-58113-576-9"]},"status":"public","title":"The Formal Execution Semantics of SpecC","year":"2002","date_updated":"2023-01-24T10:10:28Z"}]