@inproceedings{37057,
  abstract     = {{Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different abstraction levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a CAN bus model written in SystemC.}},
  author       = {{Defo, Gilles B. and Müller, Wolfgang and Kuznik, Christoph}},
  booktitle    = {{Proceedings of SIES 2010}},
  keywords     = {{Libraries, Generators, Transfer functions, Monitoring, Computational modeling, Driver circuits, Adaptation model}},
  location     = {{ Trento, Italy}},
  publisher    = {{IEEE}},
  title        = {{{Verification of a CAN Bus Model in SystemC with Functional Coverage}}},
  doi          = {{10.1109/SIES.2010.5551379}},
  year         = {{2010}},
}