@inproceedings{37009,
  abstract     = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}},
  author       = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Assertion-Based Verification of RTOS Properties}}},
  doi          = {{10.1109/DATE.2010.5457130}},
  year         = {{2010}},
}

@inproceedings{39029,
  abstract     = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}},
  author       = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}},
  booktitle    = {{Proceedings of DATE’05}},
  isbn         = {{0-7695-2288-2}},
  keywords     = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}},
  publisher    = {{IEEE}},
  title        = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}},
  doi          = {{10.1109/DATE.2005.20}},
  year         = {{2005}},
}