---
_id: '63890'
abstract:
- lang: eng
text: The computation of highly contracted electron repulsion integrals (ERIs) is
essential to achieve quantum accuracy in atomistic simulations based on quantum
mechanics. Its growing computational demands make energy efficiency a critical
concern. Recent studies demonstrate FPGAs’ superior performance and energy efficiency
for computing primitive ERIs, but the computation of highly contracted ERIs introduces
significant algorithmic complexity and new design challenges for FPGA acceleration.In
this work, we present SORCERI, the first streaming overlay acceleration for highly
contracted ERI computations on FPGAs. SORCERI introduces a novel streaming Rys
computing unit to calculate roots and weights of Rys polynomials on-chip, and
a streaming contraction unit for the contraction of primitive ERIs. This shifts
the design bottleneck from limited CPU-FPGA communication bandwidth to available
FPGA computation resources. To address practical deployment challenges for a large
number of quartet classes, we design three streaming overlays, together with an
efficient memory transpose optimization, to cover the 21 most commonly used quartet
classes in realistic atomistic simulations. To address the new computation constraints,
we use flexible calculation stages with a free-running streaming architecture
to achieve high DSP utilization and good timing closure.Experiments demonstrate
that SORCERI achieves an average 5.96x, 1.99x, and 1.16x better performance per
watt than libint on a 64-core AMD EPYC 7713 CPU, libintx on an Nvidia A40 GPU,
and SERI, the prior best-performing FPGA design for primitive ERIs. Furthermore,
SORCERI reaches a peak throughput of 44.11 GERIS (109 ERIs per second) that is
1.52x, 1.13x, and 1.93x greater than libint, libintx and SERI, respectively. SORCERI
will be released soon at https://github.com/SFU-HiAccel/SORCERI.
author:
- first_name: Philip
full_name: Stachura, Philip
last_name: Stachura
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Zhenman
full_name: Fang, Zhenman
last_name: Fang
citation:
ama: 'Stachura P, Wu X, Plessl C, Fang Z. SORCERI: Streaming Overlay Acceleration
for Highly Contracted Electron Repulsion Integral Computations in Quantum Chemistry.
In: Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable
Gate Arrays (FPGA ’26). Association for Computing Machinery; 2026:224-234.
doi:10.1145/3748173.3779198'
apa: 'Stachura, P., Wu, X., Plessl, C., & Fang, Z. (2026). SORCERI: Streaming
Overlay Acceleration for Highly Contracted Electron Repulsion Integral Computations
in Quantum Chemistry. Proceedings of the 2026 ACM/SIGDA International Symposium
on Field Programmable Gate Arrays (FPGA ’26), 224–234. https://doi.org/10.1145/3748173.3779198'
bibtex: '@inproceedings{Stachura_Wu_Plessl_Fang_2026, place={New York, NY, USA},
title={SORCERI: Streaming Overlay Acceleration for Highly Contracted Electron
Repulsion Integral Computations in Quantum Chemistry}, DOI={10.1145/3748173.3779198},
booktitle={Proceedings of the 2026 ACM/SIGDA International Symposium on Field
Programmable Gate Arrays (FPGA ’26)}, publisher={Association for Computing Machinery},
author={Stachura, Philip and Wu, Xin and Plessl, Christian and Fang, Zhenman},
year={2026}, pages={224–234} }'
chicago: 'Stachura, Philip, Xin Wu, Christian Plessl, and Zhenman Fang. “SORCERI:
Streaming Overlay Acceleration for Highly Contracted Electron Repulsion Integral
Computations in Quantum Chemistry.” In Proceedings of the 2026 ACM/SIGDA International
Symposium on Field Programmable Gate Arrays (FPGA ’26), 224–34. New York,
NY, USA: Association for Computing Machinery, 2026. https://doi.org/10.1145/3748173.3779198.'
ieee: 'P. Stachura, X. Wu, C. Plessl, and Z. Fang, “SORCERI: Streaming Overlay Acceleration
for Highly Contracted Electron Repulsion Integral Computations in Quantum Chemistry,”
in Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable
Gate Arrays (FPGA ’26), 2026, pp. 224–234, doi: 10.1145/3748173.3779198.'
mla: 'Stachura, Philip, et al. “SORCERI: Streaming Overlay Acceleration for Highly
Contracted Electron Repulsion Integral Computations in Quantum Chemistry.” Proceedings
of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
(FPGA ’26), Association for Computing Machinery, 2026, pp. 224–34, doi:10.1145/3748173.3779198.'
short: 'P. Stachura, X. Wu, C. Plessl, Z. Fang, in: Proceedings of the 2026 ACM/SIGDA
International Symposium on Field Programmable Gate Arrays (FPGA ’26), Association
for Computing Machinery, New York, NY, USA, 2026, pp. 224–234.'
date_created: 2026-02-06T06:43:22Z
date_updated: 2026-02-09T09:16:32Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3748173.3779198
keyword:
- electron repulsion integrals
- quantum chemistry
- atomistic simulation
- overlay architecture
- fpga acceleration
language:
- iso: eng
main_file_link:
- url: https://dl.acm.org/doi/10.1145/3748173.3779198
page: 224-234
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable
Gate Arrays (FPGA '26)
publication_identifier:
isbn:
- '9798400720796'
publication_status: published
publisher: Association for Computing Machinery
status: public
title: 'SORCERI: Streaming Overlay Acceleration for Highly Contracted Electron Repulsion
Integral Computations in Quantum Chemistry'
type: conference
user_id: '77439'
year: '2026'
...
---
_id: '62066'
abstract:
- lang: eng
text: In the context of high-performance computing (HPC) for distributed workloads,
individual field-programmable gate arrays (FPGAs) need efficient ways to exchange
data, which requires network infrastructure and software abstractions. Dedicated
multi-FPGA clusters provide inter-FPGA networks for direct device to device communication.
The oneAPI high-level synthesis toolchain offers I/O pipes to allow user kernels
to interact with the networking ports of the FPGA board. In this work, we evaluate
using oneAPI I/O pipes for direct FPGA-to-FPGA communication by scaling a SYCL
implementation of a Jacobi solver on up to 25 FPGAs in the Noctua 2 cluster. We
see good results in weak and strong scaling experiments.
author:
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Alt C, Plessl C, Kenter T. Evaluating oneAPI I/O Pipes in a Case Study of
Scaling a SYCL Jacobi Solver to multiple FPGAs. In: Proceedings of the 13th
International Workshop on OpenCL and SYCL. IWOCL ’25. Association for Computing
Machinery; 2025. doi:10.1145/3731125.3731131'
apa: Alt, C., Plessl, C., & Kenter, T. (2025). Evaluating oneAPI I/O Pipes in
a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs. Proceedings
of the 13th International Workshop on OpenCL and SYCL. https://doi.org/10.1145/3731125.3731131
bibtex: '@inproceedings{Alt_Plessl_Kenter_2025, place={New York, NY, USA}, series={IWOCL
’25}, title={Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi
Solver to multiple FPGAs}, DOI={10.1145/3731125.3731131},
booktitle={Proceedings of the 13th International Workshop on OpenCL and SYCL},
publisher={Association for Computing Machinery}, author={Alt, Christoph and Plessl,
Christian and Kenter, Tobias}, year={2025}, collection={IWOCL ’25} }'
chicago: 'Alt, Christoph, Christian Plessl, and Tobias Kenter. “Evaluating OneAPI
I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to Multiple FPGAs.”
In Proceedings of the 13th International Workshop on OpenCL and SYCL. IWOCL
’25. New York, NY, USA: Association for Computing Machinery, 2025. https://doi.org/10.1145/3731125.3731131.'
ieee: 'C. Alt, C. Plessl, and T. Kenter, “Evaluating oneAPI I/O Pipes in a Case
Study of Scaling a SYCL Jacobi Solver to multiple FPGAs,” 2025, doi: 10.1145/3731125.3731131.'
mla: Alt, Christoph, et al. “Evaluating OneAPI I/O Pipes in a Case Study of Scaling
a SYCL Jacobi Solver to Multiple FPGAs.” Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, 2025, doi:10.1145/3731125.3731131.
short: 'C. Alt, C. Plessl, T. Kenter, in: Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, New York, NY,
USA, 2025.'
date_created: 2025-11-04T09:45:23Z
date_updated: 2025-11-04T09:47:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3731125.3731131
keyword:
- Multi-FPGA
- High-level Synthesis
- oneAPI
- FPGA
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 13th International Workshop on OpenCL and SYCL
publication_identifier:
isbn:
- '9798400713606'
publisher: Association for Computing Machinery
quality_controlled: '1'
series_title: IWOCL ’25
status: public
title: Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver
to multiple FPGAs
type: conference
user_id: '3145'
year: '2025'
...
---
_id: '62981'
abstract:
- lang: eng
text: "Otus is a high-performance computing cluster that was launched in 2025 and
is operated by the Paderborn Center for Parallel Computing (PC2) at Paderborn
University in Germany. The system is part of the National High Performance Computing
(NHR) initiative. Otus complements the previous supercomputer Noctua 2, offering
approximately twice the computing power while retaining the three node types that
were characteristic of Noctua 2: 1) CPU compute nodes with different memory capacities,
2) high-end GPU nodes, and 3) HPC-grade FPGA nodes. On the Top500 list, which
ranks the 500 most powerful supercomputers in the world, Otus is in position 164
with the CPU partition and in position 255 with the GPU partition (June 2025).
On the Green500 list, ranking the 500 most energy-efficient supercomputers in
the world, Otus is in position 5 with the GPU partition (June 2025).\r\n\r\n\r\nThis
article provides a comprehensive overview of the system in terms of its hardware,
software, system integration, and its overall integration into the data center
building to ensure energy-efficient operation. The article aims to provide unique
insights for scientists using the system and for other centers operating HPC clusters.
The article will be continuously updated to reflect the latest system setup and
measurements. "
author:
- first_name: Sadaf
full_name: Ehtesabi, Sadaf
id: '116116'
last_name: Ehtesabi
- first_name: Manoar
full_name: Hossain, Manoar
id: '114619'
last_name: Hossain
orcid: https://orcid.org/0000-0002-0737-7981
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Andreas
full_name: Krawinkel, Andreas
id: '15275'
last_name: Krawinkel
- first_name: Lukas
full_name: Ostermann, Lukas
id: '69976'
last_name: Ostermann
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Stefan
full_name: Rohde, Stefan
id: '34009'
last_name: Rohde
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-5397
- first_name: Michael
full_name: Schwarz, Michael
id: '5312'
last_name: Schwarz
- first_name: Jens
full_name: Simon, Jens
id: '15273'
last_name: Simon
- first_name: Nils
full_name: Winnwa, Nils
id: '61189'
last_name: Winnwa
- first_name: Alex
full_name: Wiens, Alex
id: '23522'
last_name: Wiens
orcid: 0000-0003-1764-9773
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
citation:
ama: Ehtesabi S, Hossain M, Kenter T, et al. Otus Supercomputer. Vol 1. Paderborn
Center for Parallel Computing (PC2); 2025. doi:10.48550/ARXIV.2512.07401
apa: Ehtesabi, S., Hossain, M., Kenter, T., Krawinkel, A., Ostermann, L., Plessl,
C., Riebler, H., Rohde, S., Schade, R., Schwarz, M., Simon, J., Winnwa, N., Wiens,
A., & Wu, X. (2025). Otus Supercomputer (Vol. 1). Paderborn Center
for Parallel Computing (PC2). https://doi.org/10.48550/ARXIV.2512.07401
bibtex: '@book{Ehtesabi_Hossain_Kenter_Krawinkel_Ostermann_Plessl_Riebler_Rohde_Schade_Schwarz_et
al._2025, place={Paderborn}, series={PC2 Technical Report Series}, title={Otus
Supercomputer}, volume={1}, DOI={10.48550/ARXIV.2512.07401},
publisher={Paderborn Center for Parallel Computing (PC2)}, author={Ehtesabi, Sadaf
and Hossain, Manoar and Kenter, Tobias and Krawinkel, Andreas and Ostermann, Lukas
and Plessl, Christian and Riebler, Heinrich and Rohde, Stefan and Schade, Robert
and Schwarz, Michael and et al.}, year={2025}, collection={PC2 Technical Report
Series} }'
chicago: 'Ehtesabi, Sadaf, Manoar Hossain, Tobias Kenter, Andreas Krawinkel, Lukas
Ostermann, Christian Plessl, Heinrich Riebler, et al. Otus Supercomputer.
Vol. 1. PC2 Technical Report Series. Paderborn: Paderborn Center for Parallel
Computing (PC2), 2025. https://doi.org/10.48550/ARXIV.2512.07401.'
ieee: 'S. Ehtesabi et al., Otus Supercomputer, vol. 1. Paderborn:
Paderborn Center for Parallel Computing (PC2), 2025.'
mla: Ehtesabi, Sadaf, et al. Otus Supercomputer. Paderborn Center for Parallel
Computing (PC2), 2025, doi:10.48550/ARXIV.2512.07401.
short: S. Ehtesabi, M. Hossain, T. Kenter, A. Krawinkel, L. Ostermann, C. Plessl,
H. Riebler, S. Rohde, R. Schade, M. Schwarz, J. Simon, N. Winnwa, A. Wiens, X.
Wu, Otus Supercomputer, Paderborn Center for Parallel Computing (PC2), Paderborn,
2025.
date_created: 2025-12-09T09:11:04Z
date_updated: 2026-03-25T11:50:31Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: 10.48550/ARXIV.2512.07401
file:
- access_level: open_access
content_type: application/pdf
creator: deffel
date_created: 2025-12-09T09:19:12Z
date_updated: 2026-03-25T11:50:30Z
file_id: '62982'
file_name: 2512.07401v1.pdf
file_size: 4535595
relation: main_file
file_date_updated: 2026-03-25T11:50:30Z
has_accepted_license: '1'
intvolume: ' 1'
keyword:
- Otus
- Supercomputer
- FPGA
- PC2
- Paderborn Center for Parallel Computing
- Noctua 2
- HPC
language:
- iso: eng
oa: '1'
page: '33'
place: Paderborn
publication_status: published
publisher: Paderborn Center for Parallel Computing (PC2)
report_number: PC2TR-2025-1
series_title: PC2 Technical Report Series
status: public
title: Otus Supercomputer
type: report
user_id: '23522'
volume: 1
year: '2025'
...
---
_id: '53663'
abstract:
- lang: eng
text: 'Noctua 2 is a supercomputer operated at the Paderborn Center for Parallel
Computing (PC2) at Paderborn University in Germany. Noctua 2 was inaugurated in
2022 and is an Atos BullSequana XH2000 system. It consists mainly of three node
types: 1) CPU Compute nodes with AMD EPYC processors in different main memory
configurations, 2) GPU nodes with NVIDIA A100 GPUs, and 3) FPGA nodes with Xilinx
Alveo U280 and Intel Stratix 10 FPGA cards. While CPUs and GPUs are known off-the-shelf
components in HPC systems, the operation of a large number of FPGA cards from
different vendors and a dedicated FPGA-to-FPGA network are unique characteristics
of Noctua 2. This paper describes in detail the overall setup of Noctua 2 and
gives insights into the operation of the cluster from a hardware, software and
facility perspective.'
article_type: original
author:
- first_name: Carsten
full_name: Bauer, Carsten
id: '90082'
last_name: Bauer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Lukas
full_name: Mazur, Lukas
id: '90492'
last_name: Mazur
orcid: ' 0000-0001-6304-7082'
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Holger
full_name: Nitsche, Holger
id: '15272'
last_name: Nitsche
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-5397
- first_name: Michael
full_name: Schwarz, Michael
id: '5312'
last_name: Schwarz
- first_name: Nils
full_name: Winnwa, Nils
id: '61189'
last_name: Winnwa
- first_name: Alex
full_name: Wiens, Alex
id: '23522'
last_name: Wiens
orcid: 0000-0003-1764-9773
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Simon, Jens
id: '15273'
last_name: Simon
citation:
ama: Bauer C, Kenter T, Lass M, et al. Noctua 2 Supercomputer. Journal of large-scale
research facilities. 2024;9. doi:10.17815/jlsrf-8-187
apa: Bauer, C., Kenter, T., Lass, M., Mazur, L., Meyer, M., Nitsche, H., Riebler,
H., Schade, R., Schwarz, M., Winnwa, N., Wiens, A., Wu, X., Plessl, C., &
Simon, J. (2024). Noctua 2 Supercomputer. Journal of Large-Scale Research Facilities,
9. https://doi.org/10.17815/jlsrf-8-187
bibtex: '@article{Bauer_Kenter_Lass_Mazur_Meyer_Nitsche_Riebler_Schade_Schwarz_Winnwa_et
al._2024, title={Noctua 2 Supercomputer}, volume={9}, DOI={10.17815/jlsrf-8-187 }, journal={Journal of large-scale research facilities},
author={Bauer, Carsten and Kenter, Tobias and Lass, Michael and Mazur, Lukas and
Meyer, Marius and Nitsche, Holger and Riebler, Heinrich and Schade, Robert and
Schwarz, Michael and Winnwa, Nils and et al.}, year={2024} }'
chicago: Bauer, Carsten, Tobias Kenter, Michael Lass, Lukas Mazur, Marius Meyer,
Holger Nitsche, Heinrich Riebler, et al. “Noctua 2 Supercomputer.” Journal
of Large-Scale Research Facilities 9 (2024). https://doi.org/10.17815/jlsrf-8-187 .
ieee: 'C. Bauer et al., “Noctua 2 Supercomputer,” Journal of large-scale
research facilities, vol. 9, 2024, doi: 10.17815/jlsrf-8-187 .'
mla: Bauer, Carsten, et al. “Noctua 2 Supercomputer.” Journal of Large-Scale
Research Facilities, vol. 9, 2024, doi:10.17815/jlsrf-8-187 .
short: C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler,
R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal
of Large-Scale Research Facilities 9 (2024).
date_created: 2024-04-26T07:39:41Z
date_updated: 2024-04-26T08:44:30Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: '10.17815/jlsrf-8-187 '
file:
- access_level: open_access
content_type: application/pdf
creator: deffel
date_created: 2024-04-26T07:30:20Z
date_updated: 2024-04-26T08:35:17Z
file_id: '53664'
file_name: Noctua2_Supercomputer.pdf
file_size: 3825480
relation: main_file
file_date_updated: 2024-04-26T08:35:17Z
has_accepted_license: '1'
intvolume: ' 9'
keyword:
- Noctua 2
- Supercomputer
- FPGA
- PC2
- Paderborn Center for Parallel Computing
language:
- iso: eng
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Journal of large-scale research facilities
publication_status: published
status: public
title: Noctua 2 Supercomputer
type: journal_article
user_id: '8961'
volume: 9
year: '2024'
...
---
_id: '29769'
abstract:
- lang: eng
text: 'Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender
Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe
zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden
zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in
eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können
auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei
zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen
oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt
sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren
Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung
von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers
mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen
den Trojaner ``Heimtückische LUT'''' stellen wir die allererste erfolgreiche Gegenmaßnahme
vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene
direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren
ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen
für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher
bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom
in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff
zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer
vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.'
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable
systems, the defenders perspective which corresponds to the bitstream-level Trojan
detection technique, and the attackers perspective which corresponds to a novel
FPGA Trojan attack. From the defender's perspective, we introduce a first-ever
successful pre-configuration countermeasure against the ``Malicious LUT''-hardware
Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present
the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers
perspective, we present a novel attack that leverages malicious routing of the
inserted Trojan circuit to acquire a dormant state even in the generated and transmitted
bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected
in the bitstream, the presented attack can currently neither be prevented by conventional
testing and verification methods nor by bitstream-level verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University,
Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
apa: Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271
bibtex: '@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable
Computing}, DOI={10.17619/UNIPB/1-1271},
publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab},
year={2022} }'
chicago: 'Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing.
Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.'
ieee: 'Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn
University, Paderborn, Germany, 2022.'
mla: Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.
short: Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University,
Paderborn, Germany, Paderborn, 2022.
date_created: 2022-02-07T14:02:36Z
date_updated: 2022-11-30T13:39:01Z
ddc:
- '004'
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1271
has_accepted_license: '1'
keyword:
- FPGA Security
- Hardware Trojans
- Bitstream-level Trojans
- Bitstream Verification
language:
- iso: eng
main_file_link:
- open_access: '1'
url: "\turn:nbn:de:hbz:466:2-40303"
oa: '1'
place: Paderborn
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication_status: published
publisher: ' Paderborn University, Paderborn, Germany'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Trojans in Reconfigurable Computing
type: dissertation
user_id: '477'
year: '2022'
...
---
_id: '21632'
abstract:
- lang: eng
text: FPGAs have found increasing adoption in data center applications since a new
generation of high-level tools have become available which noticeably reduce development
time for FPGA accelerators and still provide high-quality results. There is, however,
no high-level benchmark suite available, which specifically enables a comparison
of FPGA architectures, programming tools, and libraries for HPC applications.
To fill this gap, we have developed an OpenCL-based open-source implementation
of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve
to analyze the current capabilities of FPGA devices, cards, and development tool
flows, track progress over time, and point out specific difficulties for FPGA
acceleration in the HPC domain. Additionally, the benchmark documents proven performance
optimization patterns. We will continue optimizing and porting the benchmark for
new generations of FPGAs and design tools and encourage active participation to
create a valuable tool for the community. To fill this gap, we have developed
an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx
and Intel FPGAs. This benchmark can serve to analyze the current capabilities
of FPGA devices, cards, and development tool flows, track progress over time,
and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally,
the benchmark documents proven performance optimization patterns. We will continue
optimizing and porting the benchmark for new generations of FPGAs and design tools
and encourage active participation to create a valuable tool for the community.
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with
a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark
Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance
Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007'
apa: Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous
High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007
bibtex: '@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007},
booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and
Plessl, Christian}, year={2020} }'
chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous
High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.
ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance
with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge
Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.'
mla: Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized
OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.”
2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable
Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.
short: 'M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop
on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.'
date_created: 2021-04-16T10:17:22Z
date_updated: 2023-09-26T11:42:53Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/h2rc51942.2020.00007
keyword:
- FPGA
- OpenCL
- High Level Synthesis
- HPC benchmarking
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/9306963
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2020 IEEE/ACM International Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)
publication_identifier:
isbn:
- '9781665415927'
publication_status: published
quality_controlled: '1'
related_material:
link:
- description: Official repository of the benchmark suite on GitHub
relation: supplementary_material
url: https://github.com/pc2/HPCC_FPGA
status: public
title: Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation
of Selected Benchmarks of the HPCChallenge Benchmark Suite
type: conference
user_id: '15278'
year: '2020'
...
---
_id: '11950'
abstract:
- lang: eng
text: Advances in electromyographic (EMG) sensor technology and machine learning
algorithms have led to an increased research effort into high density EMG-based
pattern recognition methods for prosthesis control. With the goal set on an autonomous
multi-movement prosthesis capable of performing training and classification of
an amputee’s EMG signals, the focus of this paper lies in the acceleration of
the embedded signal processing chain. We present two Xilinx Zynq-based architectures
for accelerating two inherently different high density EMG-based control algorithms.
The first hardware accelerated design achieves speed-ups of up to 4.8 over the
software-only solution, allowing for a processing delay lower than the sample
period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only
version and operates at a still satisfactory low processing delay of up to 15
ms while providing a higher reliability and robustness against electrode shift
and noisy channels.
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Florian
full_name: Kraus, Florian
last_name: Kraus
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Boschmann A, Agne A, Thombansen G, Witschen LM, Kraus F, Platzner M. Zynq-based
acceleration of robust high density myoelectric signal processing. Journal
of Parallel and Distributed Computing. 2019;123:77-89. doi:10.1016/j.jpdc.2018.07.004
apa: Boschmann, A., Agne, A., Thombansen, G., Witschen, L. M., Kraus, F., &
Platzner, M. (2019). Zynq-based acceleration of robust high density myoelectric
signal processing. Journal of Parallel and Distributed Computing, 123,
77–89. https://doi.org/10.1016/j.jpdc.2018.07.004
bibtex: '@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based
acceleration of robust high density myoelectric signal processing}, volume={123},
DOI={10.1016/j.jpdc.2018.07.004},
journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier},
author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen,
Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89}
}'
chicago: 'Boschmann, Alexander, Andreas Agne, Georg Thombansen, Linus Matthias Witschen,
Florian Kraus, and Marco Platzner. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing
123 (2019): 77–89. https://doi.org/10.1016/j.jpdc.2018.07.004.'
ieee: A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner,
“Zynq-based acceleration of robust high density myoelectric signal processing,”
Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.
mla: Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density
Myoelectric Signal Processing.” Journal of Parallel and Distributed Computing,
vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.
short: A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner,
Journal of Parallel and Distributed Computing 123 (2019) 77–89.
date_created: 2019-07-12T13:13:55Z
date_updated: 2022-01-06T06:51:13Z
department:
- _id: '78'
doi: 10.1016/j.jpdc.2018.07.004
intvolume: ' 123'
keyword:
- High density electromyography
- FPGA acceleration
- Medical signal processing
- Pattern recognition
- Prosthetics
language:
- iso: eng
page: 77-89
publication: Journal of Parallel and Distributed Computing
publication_identifier:
issn:
- 0743-7315
publication_status: published
publisher: Elsevier
status: public
title: Zynq-based acceleration of robust high density myoelectric signal processing
type: journal_article
user_id: '398'
volume: 123
year: '2019'
...
---
_id: '5417'
abstract:
- lang: eng
text: "Molecular Dynamic (MD) simulations are computationally intensive and accelerating
them using specialized hardware is a topic of investigation in many studies. One
of the routines in the critical path of MD simulations is the three-dimensional
Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using
hardware is usually bound by bandwidth and memory. Therefore, designing a high
throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn
this thesis, the feasibility of offloading FFT3d computations to FPGA implemented
using OpenCL is investigated. In order to mask the latency in memory access, an
FFT3d that overlaps computation with communication is designed. The implementa-
tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated
with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU
for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using
FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in
accelerating molecular dynamic simulations. Evaluation of CP2K simulations using
FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger
FFT3d designs."
author:
- first_name: Arjun
full_name: Ramaswami, Arjun
id: '49171'
last_name: Ramaswami
orcid: https://orcid.org/0000-0002-0909-1178
citation:
ama: Ramaswami A. Accelerating Molecular Dynamic Simulations by Offloading Fast
Fourier Transformations to FPGA. Universität Paderborn; 2018.
apa: Ramaswami, A. (2018). Accelerating Molecular Dynamic Simulations by Offloading
Fast Fourier Transformations to FPGA. Universität Paderborn.
bibtex: '@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations
by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn},
author={Ramaswami, Arjun}, year={2018} }'
chicago: Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading
Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.
ieee: A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading
Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.
mla: Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading
Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.
short: A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast
Fourier Transformations to FPGA, Universität Paderborn, 2018.
date_created: 2018-11-07T16:08:32Z
date_updated: 2022-01-12T16:32:23Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: arjunr
date_created: 2020-06-15T11:29:38Z
date_updated: 2020-06-15T11:29:38Z
file_id: '17093'
file_name: masterthesis.pdf
file_size: 1297585
relation: main_file
success: 1
file_date_updated: 2020-06-15T11:29:38Z
has_accepted_license: '1'
keyword:
- 'FFT: FPGA'
- CP2K
- OpenCL
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations
to FPGA
type: mastersthesis
user_id: '49171'
year: '2018'
...
---
_id: '10673'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Abdullah Fathi
full_name: Ahmed, Abdullah Fathi
last_name: Ahmed
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf.
Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178'
apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings. In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178
bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178},
booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
pages={1–7} }'
chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.
ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA
Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.
mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems
(AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
mappings
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10620'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring
reliability-levels of hardware designs at runtime. In: Reconfigurable Computing
and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280'
apa: 'Anwer, J., Meisner, S., & Platzner, M. (2013). Dynamic reliability management:
Reconfiguring reliability-levels of hardware designs at runtime. In Reconfigurable
Computing and FPGAs (ReConFig), 2013 International Conference on (pp. 1–6).
https://doi.org/10.1109/ReConFig.2013.6732280'
bibtex: '@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability
management: Reconfiguring reliability-levels of hardware designs at runtime},
DOI={10.1109/ReConFig.2013.6732280},
booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013},
pages={1–6} }'
chicago: 'Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability
Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.”
In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
On, 1–6, 2013. https://doi.org/10.1109/ReConFig.2013.6732280.'
ieee: 'J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring
reliability-levels of hardware designs at runtime,” in Reconfigurable Computing
and FPGAs (ReConFig), 2013 International Conference on, 2013, pp. 1–6.'
mla: 'Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels
of Hardware Designs at Runtime.” Reconfigurable Computing and FPGAs (ReConFig),
2013 International Conference On, 2013, pp. 1–6, doi:10.1109/ReConFig.2013.6732280.'
short: 'J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs
(ReConFig), 2013 International Conference On, 2013, pp. 1–6.'
date_created: 2019-07-10T09:32:57Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
doi: 10.1109/ReConFig.2013.6732280
keyword:
- fault tolerant computing
- field programmable gate arrays
- logic design
- reliability
- BYU-LANL tool
- DRM tool flow
- FPGA based hardware designs
- avionic application
- device technologies
- dynamic reliability management
- fault-tolerant operation
- hardware designs
- reconfiguring reliability levels
- space applications
- Field programmable gate arrays
- Hardware
- Redundancy
- Reliability engineering
- Runtime
- Tunneling magnetoresistance
language:
- iso: eng
page: 1-6
publication: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
on
status: public
title: 'Dynamic reliability management: Reconfiguring reliability-levels of hardware
designs at runtime'
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '2412'
abstract:
- lang: eng
text: ' Reconfigurable architectures that tightly integrate a standard CPU core
with a field-programmable hardware structure have recently been receiving impact
of these design decisions on the overall system performance is a challenging task.
In this paper, we first present a framework for the cycle-accurate performance
evaluation of hybrid reconfigurable processors on the system level. Then, we discuss
a reconfigurable processor for data-streaming applications, which attaches a coarse-grained
reconfigurable unit to the coprocessor interface of a standard embedded CPU core.
By means of a case study we evaluate the system-level impact of certain design
features for the reconfigurable unit, such as multiple contexts, register replication,
and hardware context scheduling. The results illustrate that a system-level evaluation
framework is of paramount importance for studying the architectural trade-offs
and optimizing design parameters for reconfigurable processors.'
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable
processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004
apa: Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance
evaluation of reconfigurable processors. Microprocessors and Microsystems,
29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004
bibtex: '@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation
of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004},
number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005},
pages={63–73} }'
chicago: 'Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance
Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems
29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.'
ieee: R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation
of reconfigurable processors,” Microprocessors and Microsystems, vol. 29,
no. 2–3, pp. 63–73, 2005.
mla: Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable
Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier,
2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.
short: R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005)
63–73.
date_created: 2018-04-17T14:36:10Z
date_updated: 2022-01-06T06:56:07Z
department:
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2004.06.004
intvolume: ' 29'
issue: 2-3
keyword:
- FPGA
- reconfigurable computing
- co-simulation
- Zippy
page: 63-73
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: System-level performance evaluation of reconfigurable processors
type: journal_article
user_id: '24135'
volume: 29
year: '2005'
...
---
_id: '2418'
abstract:
- lang: eng
text: ' This paper presents TKDM, a PC-based high-performance reconfigurable computing
environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual
inline memory module) bus for high-bandwidth and low-latency communication with
the host CPU. The system''s firmware is integrated with the Linux host operating
system and offers functions for data communication and FPGA reconfiguration. The
intended use of TKDM is that of a dynamically reconfigurable co-processor for
data streaming applications. The system''s firmware can be customized for specific
application domains to facilitate simple and easy-to-use programming interfaces. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory
Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE
Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755'
apa: Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor
in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology
(ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755
bibtex: '@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor
in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003},
pages={252–259} }'
chicago: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor
in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology
(ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755.
ieee: C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s
Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT),
2003, pp. 252–259.
mla: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor
in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT),
IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology
(ICFPT), IEEE Computer Society, 2003, pp. 252–259.'
date_created: 2018-04-17T15:03:34Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2003.1275755
keyword:
- coprocessor
- DIMM
- memory bus
- FPGA
- high performance computing
page: 252-259
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: TKDM – A Reconfigurable Co-processor in a PC's Memory Slot
type: conference
user_id: '24135'
year: '2003'
...
---
_id: '2421'
abstract:
- lang: eng
text: In contrast to processors, current reconfigurable devices totally lack programming
models that would allow for device independent compilation and forward compatibility.
The key to overcome this limitation is hardware virtualization. In this paper,
we resort to a macro-pipelined execution model to achieve hardware virtualization
for data streaming applications. As a hardware implementation we present a hybrid
multi-context architecture that attaches a coarse-grained reconfigurable array
to a host CPU. A co-simulation framework enables cycle-accurate simulation of
the complete architecture. As a case study we map an FIR filter to our virtualized
hardware model and evaluate different designs. We discuss the impact of the number
of contexts and the feature of context state on the speedup and the CPU load.
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable
Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL).
Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007'
apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with
Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007
bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer
Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable
Arrays}, volume={2778}, DOI={10.1007/b12007},
booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner,
Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science
(LNCS)} }'
chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware
with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science
(LNCS). Springer, 2003. https://doi.org/10.1007/b12007.
ieee: R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context
Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and
Applications (FPL), 2003, vol. 2778, pp. 151–160.
mla: Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable
Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL),
vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.
short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), Springer, 2003, pp. 151–160.'
date_created: 2018-04-17T15:11:25Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1007/b12007
intvolume: ' 2778'
keyword:
- Zippy
- multi-context
- FPGA
page: 151-160
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: Springer
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Virtualizing Hardware with Multi-Context Reconfigurable Arrays
type: conference
user_id: '24135'
volume: 2778
year: '2003'
...