---
_id: '10673'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Abdullah Fathi
full_name: Ahmed, Abdullah Fathi
last_name: Ahmed
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf.
Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178'
apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings. In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178
bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178},
booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
pages={1–7} }'
chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.
ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA
Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.
mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems
(AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
mappings
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10779'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks
scheduling and allocation. In: 25th International Conference on Field Programmable
Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994'
apa: Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time
hardware tasks scheduling and allocation. In 25th International Conference
on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994
bibtex: '@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard
real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994},
booktitle={25th International Conference on Field Programmable Logic and Applications
(FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar
and Khouas, Abdelhakim}, year={2015} }'
chicago: Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective
Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International
Conference on Field Programmable Logic and Applications (FPL). Imperial College,
2015. https://doi.org/10.1109/FPL.2015.7293994.
ieee: Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware
tasks scheduling and allocation,” in 25th International Conference on Field
Programmable Logic and Applications (FPL), 2015.
mla: Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling
and Allocation.” 25th International Conference on Field Programmable Logic
and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.
short: 'Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on
Field Programmable Logic and Applications (FPL), Imperial College, 2015.'
date_created: 2019-07-10T12:11:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPL.2015.7293994
extern: '1'
keyword:
- embedded systems
- field programmable gate arrays
- operating systems (computers)
- scheduling
- μC/OS-II
- FPGAs
- OS foundation
- SafeRTOS
- Xenomai
- chip utilization ration
- complex time constraints
- embedded systems
- hard real-time hardware task allocation
- hard real-time hardware task scheduling
- hardware-software real-time operating systems
- partially reconfigurable field-programmable gate arrays
- resource constraints
- safety-critical RTOS
- Field programmable gate arrays
- Hardware
- Job shop scheduling
- Real-time systems
- Shape
- Software
language:
- iso: eng
publication: 25th International Conference on Field Programmable Logic and Applications
(FPL)
publication_identifier:
issn:
- 1946-147X
publisher: Imperial College
status: public
title: Over effective hard real-time hardware tasks scheduling and allocation
type: conference
user_id: '398'
year: '2015'
...
---
_id: '10677'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems
(ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches:
A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf.
on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719},
booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl.
Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014,
pp. 31–37, doi:10.1109/ICES.2014.7008719.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10620'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring
reliability-levels of hardware designs at runtime. In: Reconfigurable Computing
and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280'
apa: 'Anwer, J., Meisner, S., & Platzner, M. (2013). Dynamic reliability management:
Reconfiguring reliability-levels of hardware designs at runtime. In Reconfigurable
Computing and FPGAs (ReConFig), 2013 International Conference on (pp. 1–6).
https://doi.org/10.1109/ReConFig.2013.6732280'
bibtex: '@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability
management: Reconfiguring reliability-levels of hardware designs at runtime},
DOI={10.1109/ReConFig.2013.6732280},
booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013},
pages={1–6} }'
chicago: 'Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability
Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.”
In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
On, 1–6, 2013. https://doi.org/10.1109/ReConFig.2013.6732280.'
ieee: 'J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring
reliability-levels of hardware designs at runtime,” in Reconfigurable Computing
and FPGAs (ReConFig), 2013 International Conference on, 2013, pp. 1–6.'
mla: 'Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels
of Hardware Designs at Runtime.” Reconfigurable Computing and FPGAs (ReConFig),
2013 International Conference On, 2013, pp. 1–6, doi:10.1109/ReConFig.2013.6732280.'
short: 'J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs
(ReConFig), 2013 International Conference On, 2013, pp. 1–6.'
date_created: 2019-07-10T09:32:57Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
doi: 10.1109/ReConFig.2013.6732280
keyword:
- fault tolerant computing
- field programmable gate arrays
- logic design
- reliability
- BYU-LANL tool
- DRM tool flow
- FPGA based hardware designs
- avionic application
- device technologies
- dynamic reliability management
- fault-tolerant operation
- hardware designs
- reconfiguring reliability levels
- space applications
- Field programmable gate arrays
- Hardware
- Redundancy
- Reliability engineering
- Runtime
- Tunneling magnetoresistance
language:
- iso: eng
page: 1-6
publication: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference
on
status: public
title: 'Dynamic reliability management: Reconfiguring reliability-levels of hardware
designs at runtime'
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '37007'
abstract:
- lang: eng
text: UML is widely applied for the specification and modeling of software and some
studies have demonstrated that it is applicable for HW/SW codesign. However, in
this area there is still a big gap from UML modeling to SystemC-based verification
and synthesis environments. This paper presents an efficient approach to bridge
this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework
for the seamless integration of a customized SysML entry with code generation
for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the
SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate
the applicability of our approach.
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Da
full_name: He, Da
last_name: He
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and
Simulation of Combined HW/SW Systems. In: Proceedings of DATE’10. IEEE;
2010. doi:10.1109/DATE.2010.5456990'
apa: Mischkalla, F., He, D., & Müller, W. (2010). Closing the Gap between UML-based
Modeling and Simulation of Combined HW/SW Systems. Proceedings of DATE’10.
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE
2010), Dresden. https://doi.org/10.1109/DATE.2010.5456990
bibtex: '@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing
the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems},
DOI={10.1109/DATE.2010.5456990},
booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian
and He, Da and Müller, Wolfgang}, year={2010} }'
chicago: 'Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between
UML-Based Modeling and Simulation of Combined HW/SW Systems.” In Proceedings
of DATE’10. Dresden: IEEE, 2010. https://doi.org/10.1109/DATE.2010.5456990.'
ieee: 'F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling
and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation
& Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi:
10.1109/DATE.2010.5456990.'
mla: Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and
Simulation of Combined HW/SW Systems.” Proceedings of DATE’10, IEEE, 2010,
doi:10.1109/DATE.2010.5456990.
short: 'F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden,
2010.'
conference:
location: Dresden
name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:12:35Z
date_updated: 2023-01-17T09:12:44Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456990
keyword:
- Unified modeling language
- Field programmable gate arrays
- Bridges
- Helium
- Real time systems
- Operating systems
- Documentation
- Application software
- XML
- Space exploration
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
eisbn:
- 978-3-9810801-6-2
publisher: IEEE
status: public
title: Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW
Systems
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '6508'
abstract:
- lang: eng
text: 'In this paper, we present a framework that supports experimenting with evolutionary
hardware design. We describe the framework''s modules for composing evolutionary
optimizers and for setting up, controlling, and analyzing experiments. Two case
studies demonstrate the usefulness of the framework: evolution of hash functions
and evolution based on pre-engineered circuits.'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution.
In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).
IEEE; 2007:447-454. doi:10.1109/ahs.2007.73'
apa: 'Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware
Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73'
bibtex: '@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework
for Hardware Evolution}, DOI={10.1109/ahs.2007.73},
booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)},
publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454}
}'
chicago: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems
(AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73.'
ieee: 'P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,”
in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007),
Edinburgh, UK, 2007, pp. 447–454.'
mla: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.'
short: 'P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware
and Systems (AHS 2007), IEEE, 2007, pp. 447–454.'
conference:
end_date: 2007-08-08
location: Edinburgh, UK
name: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
start_date: 2007-08-05
date_created: 2019-01-08T09:52:43Z
date_updated: 2022-01-06T07:03:08Z
department:
- _id: '78'
doi: 10.1109/ahs.2007.73
keyword:
- integrated circuit design
- hardware evolution
- evolutionary hardware design
- evolutionary optimizers
- hash functions
- preengineered circuits
- Hardware
- Circuits
- Design optimization
- Visualization
- Genetic programming
- Genetic mutations
- Clustering algorithms
- Biological cells
- Field programmable gate arrays
- Routing
language:
- iso: eng
page: 447-454
publication: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
publication_identifier:
isbn:
- 076952866X
- '9780769528663'
publication_status: published
publisher: IEEE
status: public
title: 'MOVES: A Modular Framework for Hardware Evolution'
type: conference
user_id: '3118'
year: '2007'
...
---
_id: '39029'
abstract:
- lang: eng
text: UML 2.0 provides a rich set of diagrams for systems documentation and specification.
Much effort has been undertaken to employ different aspects of UML for multiple
domains, mainly in the area of software systems. Considering the area of electronic
design automation, however, we currently see only very few approaches which investigate
UML for hardware design and hardware/software co-design. We present an approach
for executable UML closing the gap from system specification to its model-based
execution on reconfigurable hardware. For this purpose, we present our abstract
execution platform (AEP), which is based on a virtual machine running an executable
UML subset for embedded software and reconfigurable hardware. This subset combines
UML 2.0 classes, state-machines and sequence diagrams for a complete system specification.
We describe how these binary encoded UML specifications can be directly executed
and give the implementation of such a virtual machine on a Virtex II FPGA. Finally,
we present evaluation results comparing the AEP implementation with C code on
a C167 microcontroller.
author:
- first_name: Tim
full_name: Schattkowsky, Tim
last_name: Schattkowsky
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Achim
full_name: Rettberg, Achim
last_name: Rettberg
citation:
ama: 'Schattkowsky T, Müller W, Rettberg A. A Model-Based Approach for Executable
Specification on Reconfigurable Hardware. In: Proceedings of DATE’05. IEEE;
2005. doi:10.1109/DATE.2005.20'
apa: Schattkowsky, T., Müller, W., & Rettberg, A. (2005). A Model-Based Approach
for Executable Specification on Reconfigurable Hardware. Proceedings of DATE’05.
https://doi.org/10.1109/DATE.2005.20
bibtex: '@inproceedings{Schattkowsky_Müller_Rettberg_2005, place={Munich, Germany
}, title={A Model-Based Approach for Executable Specification on Reconfigurable
Hardware}, DOI={10.1109/DATE.2005.20},
booktitle={Proceedings of DATE’05}, publisher={IEEE}, author={Schattkowsky, Tim
and Müller, Wolfgang and Rettberg, Achim}, year={2005} }'
chicago: 'Schattkowsky, Tim, Wolfgang Müller, and Achim Rettberg. “A Model-Based
Approach for Executable Specification on Reconfigurable Hardware.” In Proceedings
of DATE’05. Munich, Germany : IEEE, 2005. https://doi.org/10.1109/DATE.2005.20.'
ieee: 'T. Schattkowsky, W. Müller, and A. Rettberg, “A Model-Based Approach for
Executable Specification on Reconfigurable Hardware,” 2005, doi: 10.1109/DATE.2005.20.'
mla: Schattkowsky, Tim, et al. “A Model-Based Approach for Executable Specification
on Reconfigurable Hardware.” Proceedings of DATE’05, IEEE, 2005, doi:10.1109/DATE.2005.20.
short: 'T. Schattkowsky, W. Müller, A. Rettberg, in: Proceedings of DATE’05, IEEE,
Munich, Germany , 2005.'
date_created: 2023-01-24T08:10:40Z
date_updated: 2023-01-24T08:10:44Z
department:
- _id: '672'
doi: 10.1109/DATE.2005.20
keyword:
- Hardware
- Unified modeling language
- Virtual machining
- Object oriented modeling
- Field programmable gate arrays
- Java
- Microcontrollers
- Embedded software
- Real time systems
- Documentation
language:
- iso: eng
place: 'Munich, Germany '
publication: Proceedings of DATE’05
publication_identifier:
isbn:
- 0-7695-2288-2
publisher: IEEE
status: public
title: A Model-Based Approach for Executable Specification on Reconfigurable Hardware
type: conference
user_id: '5786'
year: '2005'
...