---
_id: '26746'
abstract:
- lang: eng
text: "Previous research in proof-carrying hardware has established the feasibility
and utility of the approach, and provided a concrete solution for employing it
for the certification of functional equivalence checking against a specification,
but fell short in connecting it to state-of-the-art formal verification insights,
methods and tools. Due to the immense complexity of modern circuits, and verification
challenges such as the state explosion problem for sequential circuits, this restriction
of readily-available verification solutions severely limited the applicability
of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the
PCH approach and current advances in formal hardware verification, provides methods
and tools to express and certify a wide range of circuit properties, both functional
and non-functional, and presents for the first time prototypes in which circuits
that are implemented on actual reconfigurable hardware are verified with PCH methods.
Using these results, designers can now apply PCH to establish trust in more complex
circuits, by using more diverse properties which they can express using modern,
efficient property specification techniques."
- lang: ger
text: "Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit
und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen
Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen,
Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund
der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der
Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung
sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem
größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen
PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden
und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite
von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale.
Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels
PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert
sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen
in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt
von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt
werden können."
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University; 2021.
apa: Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn University.
bibtex: '@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties
of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn
University}, author={Wiersema, Tobias}, year={2021} }'
chicago: 'Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
ieee: 'T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
mla: Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University, 2021.
short: T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
date_created: 2021-10-25T06:35:41Z
date_updated: 2022-01-06T06:57:26Z
ddc:
- '006'
department:
- _id: '78'
keyword:
- Proof-Carrying Hardware
- Formal Verification
- Sequential Circuits
- Non-Functional Properties
- Functional Properties
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800
oa: '1'
page: '293'
place: Paderborn
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication_status: published
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying
Hardware
type: dissertation
user_id: '3118'
year: '2021'
...
---
_id: '17358'
abstract:
- lang: eng
text: 'Approximate circuits trade-off computational accuracy against improvements
in hardware area, delay, or energy consumption. IP core vendors who wish to create
such circuits need to convince consumers of the resulting approximation quality.
As a solution we propose proof-carrying approximate circuits: The vendor creates
an approximate IP core together with a certificate that proves the approximation
quality. The proof certificate is bundled with the approximate IP core and sent
off to the consumer. The consumer can formally verify the approximation quality
of the IP core at a fraction of the typical computational cost for formal verification.
In this paper, we first make the case for proof-carrying approximate circuits
and then demonstrate the feasibility of the approach by a set of synthesis experiments
using an exemplary approximation framework.'
article_type: original
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE
Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088.
doi:10.1109/TVLSI.2020.3008061
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate
Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9),
2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061
bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate
Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061},
number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems},
publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner,
Marco}, year={2020}, pages={2084–2088} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems
28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.'
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate
Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol.
28, no. 9, pp. 2084–2088, 2020.
mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE
Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE,
2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.
short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large
Scale Integration Systems 28 (2020) 2084–2088.
date_created: 2020-07-06T11:21:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
doi: 10.1109/TVLSI.2020.3008061
funded_apc: '1'
intvolume: ' 28'
issue: '9'
keyword:
- Approximate circuit synthesis
- approximate computing
- error metrics
- formal verification
- proof-carrying hardware
language:
- iso: eng
page: 2084 - 2088
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: IEEE Transactions On Very Large Scale Integration Systems
publication_identifier:
eissn:
- 1557-9999
issn:
- 1063-8210
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Proof-carrying Approximate Circuits
type: journal_article
user_id: '49051'
volume: 28
year: '2020'
...
---
_id: '1097'
author:
- first_name: Felix Paul
full_name: Jentzsch, Felix Paul
last_name: Jentzsch
citation:
ama: Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security
Monitors. Universität Paderborn; 2018.
apa: Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn.
bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with
Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch,
Felix Paul}, year={2018} }'
chicago: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
ieee: F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
mla: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security
Monitors, Universität Paderborn, 2018.
date_created: 2018-01-15T16:48:05Z
date_updated: 2022-01-06T06:50:54Z
department:
- _id: '78'
keyword:
- Approximate Computing
- Proof-Carrying Hardware
- Formal Verification
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: Enforcing IP Core Connection Properties with Verifiable Security Monitors
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '39069'
abstract:
- lang: eng
text: We present the syntax and semantics of a past- and future-oriented temporal
extension of the Object Constraint Language (OCL). Our extension supports designers
to express time-bounded properties over a state-oriented UML model of a system
under development. The semantics is formally defined over the system states of
a mathematical object model. Additionally, we present a mapping to Clocked Linear
Temporal Logic (Clocked LTL) formulae, which is the basis for further application
in verification with model checking. We demonstrate the applicability of the approach
by the example of a buffer specification in the context of a production system.
author:
- first_name: Stephan
full_name: Flake, Stephan
last_name: Flake
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Flake S, Müller W. Past- and Future-Oriented Time-Bound Temporal Properties
with OCL. In: Proceedings of SEFM´04. IEEE; 2004. doi:10.1109/SEFM.2004.1347516'
apa: Flake, S., & Müller, W. (2004). Past- and Future-Oriented Time-Bound Temporal
Properties with OCL. Proceedings of SEFM´04. Proceedings of the Second
International Conference on Software Engineering and Formal Methods. https://doi.org/10.1109/SEFM.2004.1347516
bibtex: '@inproceedings{Flake_Müller_2004, place={Beijing, China}, title={Past-
and Future-Oriented Time-Bound Temporal Properties with OCL}, DOI={10.1109/SEFM.2004.1347516},
booktitle={Proceedings of SEFM´04}, publisher={IEEE}, author={Flake, Stephan and
Müller, Wolfgang}, year={2004} }'
chicago: 'Flake, Stephan, and Wolfgang Müller. “Past- and Future-Oriented Time-Bound
Temporal Properties with OCL.” In Proceedings of SEFM´04. Beijing, China:
IEEE, 2004. https://doi.org/10.1109/SEFM.2004.1347516.'
ieee: 'S. Flake and W. Müller, “Past- and Future-Oriented Time-Bound Temporal Properties
with OCL,” presented at the Proceedings of the Second International Conference
on Software Engineering and Formal Methods, 2004, doi: 10.1109/SEFM.2004.1347516.'
mla: Flake, Stephan, and Wolfgang Müller. “Past- and Future-Oriented Time-Bound
Temporal Properties with OCL.” Proceedings of SEFM´04, IEEE, 2004, doi:10.1109/SEFM.2004.1347516.
short: 'S. Flake, W. Müller, in: Proceedings of SEFM´04, IEEE, Beijing, China, 2004.'
conference:
name: ' Proceedings of the Second International Conference on Software Engineering
and Formal Methods'
date_created: 2023-01-24T09:03:36Z
date_updated: 2023-01-24T09:03:41Z
department:
- _id: '672'
doi: 10.1109/SEFM.2004.1347516
keyword:
- Unified modeling language
- Logic
- Clocks
- Boolean functions
- Application software
- Time factors
- Real time systems
- Formal verification
- Buffer storage
- Software packages
language:
- iso: eng
place: Beijing, China
publication: Proceedings of SEFM´04
publication_identifier:
isbn:
- 0-7695-2222-X
publisher: IEEE
status: public
title: Past- and Future-Oriented Time-Bound Temporal Properties with OCL
type: conference
user_id: '5786'
year: '2004'
...
---
_id: '39382'
abstract:
- lang: eng
text: We present a rigorous but transparent semantics definition of the SpecC language
that covers the execution of SpecC behaviors and their interaction with the kernel
process. The semantics include wait, wait for, par, and try statements as they
are introduced in SpecC. We present our definition in form of distributed abstract
state machine (ASM) rules strictly following the lines of the SpecC Language Reference
Manual. We mainly see our formal semantics in three application areas. First,
it is a concise, unambiguous description for documentation and standardization.
Second, it applies as a high-level, pseudo code-oriented specification for the
implementation of a SpecC simulator. Finally, it is a first step for SpecC synthesis
in order to identify similar concepts with other languages like VHDL and SystemC
for the definition of common patterns and language subsets.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Rainer
full_name: Dömer, Rainer
last_name: Dömer
- first_name: Andreas
full_name: Gerstlauer, Andreas
last_name: Gerstlauer
citation:
ama: 'Müller W, Dömer R, Gerstlauer A. The Formal Execution Semantics of SpecC.
In: Proceedings of the ISSS02. ; 2002. doi:10.1145/581199.581234 '
apa: Müller, W., Dömer, R., & Gerstlauer, A. (2002). The Formal Execution Semantics
of SpecC. Proceedings of the ISSS02. https://doi.org/10.1145/581199.581234
bibtex: '@inproceedings{Müller_Dömer_Gerstlauer_2002, place={Nagoya, Japan}, title={The
Formal Execution Semantics of SpecC}, DOI={10.1145/581199.581234 }, booktitle={Proceedings of the ISSS02}, author={Müller,
Wolfgang and Dömer, Rainer and Gerstlauer, Andreas}, year={2002} }'
chicago: Müller, Wolfgang, Rainer Dömer, and Andreas Gerstlauer. “The Formal Execution
Semantics of SpecC.” In Proceedings of the ISSS02. Nagoya, Japan, 2002.
https://doi.org/10.1145/581199.581234
.
ieee: 'W. Müller, R. Dömer, and A. Gerstlauer, “The Formal Execution Semantics of
SpecC,” 2002, doi: 10.1145/581199.581234
.'
mla: Müller, Wolfgang, et al. “The Formal Execution Semantics of SpecC.” Proceedings
of the ISSS02, 2002, doi:10.1145/581199.581234
.
short: 'W. Müller, R. Dömer, A. Gerstlauer, in: Proceedings of the ISSS02, Nagoya,
Japan, 2002.'
date_created: 2023-01-24T10:10:24Z
date_updated: 2023-01-24T10:10:28Z
department:
- _id: '672'
doi: '10.1145/581199.581234 '
keyword:
- Standardization
- Kernel
- Permission
- Formal verification
- Logic functions
- Documentation
- Reasoning about programs
- Specification languages
- Formal specifications
- Software systems
language:
- iso: eng
place: Nagoya, Japan
publication: Proceedings of the ISSS02
publication_identifier:
isbn:
- 1-58113-576-9
status: public
title: The Formal Execution Semantics of SpecC
type: conference
user_id: '5786'
year: '2002'
...
---
_id: '39403'
abstract:
- lang: eng
text: The Unified Modeling Language (UML) has received wide acceptance as a standard
language in the field of software specification by means of different diagram
types. In a recent version of UML, the textual Object Constraint Language (OCL)
was introduced to support specification of constraints for UML models. But OCL
currently does not provide sufficient means to specify constraints over the dynamic
behavior of a model. This article presents an OCL extension that is consistent
with current OCL and enables modelers to specify state-related time-bounded constraints.
We consider the case study of a flexible manufacturing system and identify typical
real-time constraints. The constraints are presented in our temporal OCL extension
as well as in temporal logic formulae. For general application, we define a semantics
of our OCL extension by means of a time-bounded temporal logic based on Computational
Tree Logic (CTL).
author:
- first_name: Stephan
full_name: Flake, Stephan
last_name: Flake
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Flake S, Müller W. Specification of Real-Time Properties for UML Models. In:
Proceedings of HICSS-35. ; 2002. doi:10.1109/HICSS.2002.994469'
apa: Flake, S., & Müller, W. (2002). Specification of Real-Time Properties for
UML Models. Proceedings of HICSS-35. Proceedings of the 35th Annual Hawaii
International Conference on System Sciences, Big Island, HI, USA . https://doi.org/10.1109/HICSS.2002.994469
bibtex: '@inproceedings{Flake_Müller_2002, place={Big Island, HI, USA }, title={Specification
of Real-Time Properties for UML Models}, DOI={10.1109/HICSS.2002.994469},
booktitle={Proceedings of HICSS-35}, author={Flake, Stephan and Müller, Wolfgang},
year={2002} }'
chicago: Flake, Stephan, and Wolfgang Müller. “Specification of Real-Time Properties
for UML Models.” In Proceedings of HICSS-35. Big Island, HI, USA , 2002.
https://doi.org/10.1109/HICSS.2002.994469.
ieee: 'S. Flake and W. Müller, “Specification of Real-Time Properties for UML Models,”
presented at the Proceedings of the 35th Annual Hawaii International Conference
on System Sciences, Big Island, HI, USA , 2002, doi: 10.1109/HICSS.2002.994469.'
mla: Flake, Stephan, and Wolfgang Müller. “Specification of Real-Time Properties
for UML Models.” Proceedings of HICSS-35, 2002, doi:10.1109/HICSS.2002.994469.
short: 'S. Flake, W. Müller, in: Proceedings of HICSS-35, Big Island, HI, USA ,
2002.'
conference:
location: 'Big Island, HI, USA '
name: Proceedings of the 35th Annual Hawaii International Conference on System Sciences
date_created: 2023-01-24T10:22:12Z
date_updated: 2023-01-24T10:22:16Z
department:
- _id: '672'
doi: 10.1109/HICSS.2002.994469
keyword:
- Unified modeling language
- Logic
- Formal verification
- Real time systems
- Programming profession
- Vehicle dynamics
- Software standards
- Flexible manufacturing systems
- Electronics industry
- Protocols
language:
- iso: eng
place: 'Big Island, HI, USA '
publication: Proceedings of HICSS-35
publication_identifier:
isbn:
- 0-7695-1435-9
status: public
title: Specification of Real-Time Properties for UML Models
type: conference
user_id: '5786'
year: '2002'
...
---
_id: '39421'
abstract:
- lang: eng
text: We present a rigorous but transparent semantics definition of SystemC that
covers method, thread, and clocked thread behavior as well as their interaction
with the simulation kernel process. The semantics includes watching statements,
signal assignment, and wait statements as they are introduced in SystemC V1.O.
We present our definition in form of distributed Abstract State Machines (ASMs)
rules reflecting the view given in the SystemC User's Manual and the reference
implementation. We mainly see our formal semantics as a concise, unambiguous,
high-level specification for SystemC-based implementations and for standardization.
Additionally, it can be used as a sound basis to investigate SystemC interoperability
with Verilog and VHDL.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Jürgen
full_name: Ruf, Jürgen
last_name: Ruf
- first_name: D. W.
full_name: Hoffmann, D. W.
last_name: Hoffmann
- first_name: Joachim
full_name: Gerlach, Joachim
last_name: Gerlach
- first_name: Thomas
full_name: Kropf, Thomas
last_name: Kropf
- first_name: W.
full_name: Rosenstiehl, W.
last_name: Rosenstiehl
citation:
ama: 'Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation
Semantics of SystemC. In: Proceedings of the Design, Automation, and Test in
Europe (DATE’01). IEEE; 2001. doi:10.1109/DATE.2001.915002'
apa: Müller, W., Ruf, J., Hoffmann, D. W., Gerlach, J., Kropf, T., & Rosenstiehl,
W. (2001). The Simulation Semantics of SystemC. Proceedings of the Design,
Automation, and Test in Europe (DATE’01). Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001. https://doi.org/10.1109/DATE.2001.915002
bibtex: '@inproceedings{Müller_Ruf_Hoffmann_Gerlach_Kropf_Rosenstiehl_2001, place={Munich,
Germany }, title={The Simulation Semantics of SystemC}, DOI={10.1109/DATE.2001.915002},
booktitle={Proceedings of the Design, Automation, and Test in Europe (DATE’01)},
publisher={IEEE}, author={Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W.
and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}, year={2001} }'
chicago: 'Müller, Wolfgang, Jürgen Ruf, D. W. Hoffmann, Joachim Gerlach, Thomas
Kropf, and W. Rosenstiehl. “The Simulation Semantics of SystemC.” In Proceedings
of the Design, Automation, and Test in Europe (DATE’01). Munich, Germany :
IEEE, 2001. https://doi.org/10.1109/DATE.2001.915002.'
ieee: 'W. Müller, J. Ruf, D. W. Hoffmann, J. Gerlach, T. Kropf, and W. Rosenstiehl,
“The Simulation Semantics of SystemC,” presented at the Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001, 2001, doi: 10.1109/DATE.2001.915002.'
mla: Müller, Wolfgang, et al. “The Simulation Semantics of SystemC.” Proceedings
of the Design, Automation, and Test in Europe (DATE’01), IEEE, 2001, doi:10.1109/DATE.2001.915002.
short: 'W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl,
in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE,
Munich, Germany , 2001.'
conference:
name: ' Proceedings Design, Automation and Test in Europe. Conference and Exhibition
2001'
date_created: 2023-01-24T10:39:33Z
date_updated: 2023-01-24T10:39:38Z
department:
- _id: '672'
doi: 10.1109/DATE.2001.915002
keyword:
- Yarn
- Formal verification
- Kernel
- Hardware design languages
- Electronic design automation and methodology
- Algebra
- Computational modeling
- Logic functions
- Computer languages
- Clocks
language:
- iso: eng
place: 'Munich, Germany '
publication: Proceedings of the Design, Automation, and Test in Europe (DATE’01)
publication_identifier:
isbn:
- 0-7695-0993-2
publisher: IEEE
status: public
title: The Simulation Semantics of SystemC
type: conference
user_id: '5786'
year: '2001'
...
---
_id: '34448'
abstract:
- lang: eng
text: We present a rigorous but transparent semantic definition for VHDL corresponding
to the IEEE VHDL’ 93 standard [68, 9, 84]. Our definition covers the full behavior
of signal and variable assignments as well as the behavior of the various wait
statements including delta, time, and postponed cycles. We consider explicitly
declared signals, ports, local variables, and shared variables. Our specification
defines an abstract VHDL ’ 93 interpreter in the form of transition rules for
an evolving algebra machine (EA-Machine) [60]. It faithfully reflects and supports
the view of simulation given in the IEEE VHDL ’ 93 standard language reference
manual. The definition can be understood without any prior formal training. We
illustrate our definition by running the example VHDL program set out in the Introduction
to this volume.
author:
- first_name: Egon
full_name: Börger, Egon
last_name: Börger
- first_name: Uwe
full_name: Glässer, Uwe
last_name: Glässer
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Börger E, Glässer U, Müller W. A Formal Definition of an Abstract VHDL’93
Simulator by EA-Machines. In: Delgado Kloos C, Breuer PT, eds. Semantics of
VHDL. Kluwer Academic Publishers; 1995:107-139. doi:10.1007/978-1-4615-2237-9_5'
apa: Börger, E., Glässer, U., & Müller, W. (1995). A Formal Definition of an
Abstract VHDL’93 Simulator by EA-Machines. In C. Delgado Kloos & P. T. Breuer
(Eds.), Semantics of VHDL (pp. 107–139). Kluwer Academic Publishers. https://doi.org/10.1007/978-1-4615-2237-9_5
bibtex: '@inbook{Börger_Glässer_Müller_1995, place={Dordrecht}, title={A Formal
Definition of an Abstract VHDL’93 Simulator by EA-Machines}, DOI={10.1007/978-1-4615-2237-9_5},
booktitle={Semantics of VHDL}, publisher={Kluwer Academic Publishers}, author={Börger,
Egon and Glässer, Uwe and Müller, Wolfgang}, editor={Delgado Kloos, C. and Breuer,
Peter T.}, year={1995}, pages={107–139} }'
chicago: 'Börger, Egon, Uwe Glässer, and Wolfgang Müller. “A Formal Definition of
an Abstract VHDL’93 Simulator by EA-Machines.” In Semantics of VHDL, edited
by C. Delgado Kloos and Peter T. Breuer, 107–39. Dordrecht: Kluwer Academic Publishers,
1995. https://doi.org/10.1007/978-1-4615-2237-9_5.'
ieee: 'E. Börger, U. Glässer, and W. Müller, “A Formal Definition of an Abstract
VHDL’93 Simulator by EA-Machines,” in Semantics of VHDL, C. Delgado Kloos
and P. T. Breuer, Eds. Dordrecht: Kluwer Academic Publishers, 1995, pp. 107–139.'
mla: Börger, Egon, et al. “A Formal Definition of an Abstract VHDL’93 Simulator
by EA-Machines.” Semantics of VHDL, edited by C. Delgado Kloos and Peter
T. Breuer, Kluwer Academic Publishers, 1995, pp. 107–39, doi:10.1007/978-1-4615-2237-9_5.
short: 'E. Börger, U. Glässer, W. Müller, in: C. Delgado Kloos, P.T. Breuer (Eds.),
Semantics of VHDL, Kluwer Academic Publishers, Dordrecht, 1995, pp. 107–139.'
date_created: 2022-12-15T11:42:48Z
date_updated: 2022-12-15T11:43:14Z
department:
- _id: '672'
doi: 10.1007/978-1-4615-2237-9_5
editor:
- first_name: C.
full_name: Delgado Kloos, C.
last_name: Delgado Kloos
- first_name: Peter T.
full_name: Breuer, Peter T.
last_name: Breuer
keyword:
- Transition Rule Formal Verification Variable Assignment Kernel Process Simulation
Cycle
language:
- iso: eng
page: 107 - 139
place: Dordrecht
publication: Semantics of VHDL
publication_identifier:
isbn:
- 978-1-4615-2237-9
publisher: Kluwer Academic Publishers
status: public
title: A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines
type: book_chapter
user_id: '5786'
year: '1995'
...