[{"language":[{"iso":"eng"}],"ddc":["004"],"keyword":["Otus","Supercomputer","FPGA","PC2","Paderborn Center for Parallel Computing","Noctua 2","HPC"],"report_number":"PC2TR-2025-1","file":[{"content_type":"application/pdf","relation":"main_file","creator":"deffel","date_created":"2025-12-09T09:19:12Z","date_updated":"2026-03-25T11:50:30Z","file_name":"2512.07401v1.pdf","file_id":"62982","access_level":"open_access","file_size":4535595}],"abstract":[{"text":"Otus is a high-performance computing cluster that was launched in 2025 and is operated by the Paderborn Center for Parallel Computing (PC2) at Paderborn University in Germany. The system is part of the National High Performance Computing (NHR) initiative. Otus complements the previous supercomputer Noctua 2, offering approximately twice the computing power while retaining the three node types that were characteristic of Noctua 2: 1) CPU compute nodes with different memory capacities, 2) high-end GPU nodes, and 3) HPC-grade FPGA nodes. On the Top500 list, which ranks the 500 most powerful supercomputers in the world, Otus is in position 164 with the CPU partition and in position 255 with the GPU partition (June 2025). On the Green500 list, ranking the 500 most energy-efficient supercomputers in the world, Otus is in position 5 with the GPU partition (June 2025).\r\n\r\n\r\nThis article provides a comprehensive overview of the system in terms of its hardware, software, system integration, and its overall integration into the data center building to ensure energy-efficient operation. The article aims to provide unique insights for scientists using the system and for other centers operating HPC clusters. The article will be continuously updated to reflect the latest system setup and measurements. ","lang":"eng"}],"date_created":"2025-12-09T09:11:04Z","publisher":"Paderborn Center for Parallel Computing (PC2)","title":"Otus Supercomputer","year":"2025","user_id":"23522","series_title":"PC2 Tech­nic­al Re­port Series","department":[{"_id":"27"},{"_id":"518"}],"_id":"62981","file_date_updated":"2026-03-25T11:50:30Z","type":"report","status":"public","author":[{"id":"116116","full_name":"Ehtesabi, Sadaf","last_name":"Ehtesabi","first_name":"Sadaf"},{"first_name":"Manoar","last_name":"Hossain","orcid":"https://orcid.org/0000-0002-0737-7981","id":"114619","full_name":"Hossain, Manoar"},{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"full_name":"Krawinkel, Andreas","id":"15275","last_name":"Krawinkel","first_name":"Andreas"},{"first_name":"Lukas","last_name":"Ostermann","full_name":"Ostermann, Lukas","id":"69976"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"first_name":"Stefan","last_name":"Rohde","full_name":"Rohde, Stefan","id":"34009"},{"first_name":"Robert","id":"75963","full_name":"Schade, Robert","last_name":"Schade","orcid":"0000-0002-6268-5397"},{"first_name":"Michael","last_name":"Schwarz","full_name":"Schwarz, Michael","id":"5312"},{"first_name":"Jens","last_name":"Simon","id":"15273","full_name":"Simon, Jens"},{"last_name":"Winnwa","full_name":"Winnwa, Nils","id":"61189","first_name":"Nils"},{"first_name":"Alex","last_name":"Wiens","orcid":"0000-0003-1764-9773","id":"23522","full_name":"Wiens, Alex"},{"id":"77439","full_name":"Wu, Xin","last_name":"Wu","first_name":"Xin"}],"volume":1,"oa":"1","date_updated":"2026-03-25T11:50:31Z","doi":"10.48550/ARXIV.2512.07401","publication_status":"published","has_accepted_license":"1","citation":{"short":"S. Ehtesabi, M. Hossain, T. Kenter, A. Krawinkel, L. Ostermann, C. Plessl, H. Riebler, S. Rohde, R. Schade, M. Schwarz, J. Simon, N. Winnwa, A. Wiens, X. Wu, Otus Supercomputer, Paderborn Center for Parallel Computing (PC2), Paderborn, 2025.","mla":"Ehtesabi, Sadaf, et al. <i>Otus Supercomputer</i>. Paderborn Center for Parallel Computing (PC2), 2025, doi:<a href=\"https://doi.org/10.48550/ARXIV.2512.07401\">10.48550/ARXIV.2512.07401</a>.","bibtex":"@book{Ehtesabi_Hossain_Kenter_Krawinkel_Ostermann_Plessl_Riebler_Rohde_Schade_Schwarz_et al._2025, place={Paderborn}, series={PC2 Tech­nic­al Re­port Series}, title={Otus Supercomputer}, volume={1}, DOI={<a href=\"https://doi.org/10.48550/ARXIV.2512.07401\">10.48550/ARXIV.2512.07401</a>}, publisher={Paderborn Center for Parallel Computing (PC2)}, author={Ehtesabi, Sadaf and Hossain, Manoar and Kenter, Tobias and Krawinkel, Andreas and Ostermann, Lukas and Plessl, Christian and Riebler, Heinrich and Rohde, Stefan and Schade, Robert and Schwarz, Michael and et al.}, year={2025}, collection={PC2 Tech­nic­al Re­port Series} }","apa":"Ehtesabi, S., Hossain, M., Kenter, T., Krawinkel, A., Ostermann, L., Plessl, C., Riebler, H., Rohde, S., Schade, R., Schwarz, M., Simon, J., Winnwa, N., Wiens, A., &#38; Wu, X. (2025). <i>Otus Supercomputer</i> (Vol. 1). Paderborn Center for Parallel Computing (PC2). <a href=\"https://doi.org/10.48550/ARXIV.2512.07401\">https://doi.org/10.48550/ARXIV.2512.07401</a>","chicago":"Ehtesabi, Sadaf, Manoar Hossain, Tobias Kenter, Andreas Krawinkel, Lukas Ostermann, Christian Plessl, Heinrich Riebler, et al. <i>Otus Supercomputer</i>. Vol. 1. PC2 Tech­nic­al Re­port Series. Paderborn: Paderborn Center for Parallel Computing (PC2), 2025. <a href=\"https://doi.org/10.48550/ARXIV.2512.07401\">https://doi.org/10.48550/ARXIV.2512.07401</a>.","ieee":"S. Ehtesabi <i>et al.</i>, <i>Otus Supercomputer</i>, vol. 1. Paderborn: Paderborn Center for Parallel Computing (PC2), 2025.","ama":"Ehtesabi S, Hossain M, Kenter T, et al. <i>Otus Supercomputer</i>. Vol 1. Paderborn Center for Parallel Computing (PC2); 2025. doi:<a href=\"https://doi.org/10.48550/ARXIV.2512.07401\">10.48550/ARXIV.2512.07401</a>"},"intvolume":"         1","page":"33","place":"Paderborn"},{"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"doi":"10.1109/h2rc51942.2020.00007","date_updated":"2023-09-26T11:42:53Z","author":[{"id":"40778","full_name":"Meyer, Marius","last_name":"Meyer","first_name":"Marius"},{"full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"citation":{"ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>. ; 2020. doi:<a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: <a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>.","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2020. <a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">https://doi.org/10.1109/h2rc51942.2020.00007</a>.","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={<a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2020, doi:<a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>.","apa":"Meyer, M., Kenter, T., &#38; Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>. <a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">https://doi.org/10.1109/h2rc51942.2020.00007</a>"},"publication_status":"published","publication_identifier":{"isbn":["9781665415927"]},"related_material":{"link":[{"url":"https://github.com/pc2/HPCC_FPGA","relation":"supplementary_material","description":"Official repository of the benchmark suite on GitHub"}]},"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"21632","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"status":"public","type":"conference","title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","date_created":"2021-04-16T10:17:22Z","year":"2020","quality_controlled":"1","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community."}],"publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)"}]