@article{53213,
  author       = {{Amiri, Arman and Tavana, Madjid and Arman, Hosein}},
  issn         = {{2542-6605}},
  journal      = {{Internet of Things}},
  keywords     = {{Management of Technology and Innovation, Artificial Intelligence, Computer Science Applications, Hardware and Architecture, Engineering (miscellaneous), Information Systems, Computer Science (miscellaneous), Software}},
  publisher    = {{Elsevier BV}},
  title        = {{{An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction}}},
  doi          = {{10.1016/j.iot.2023.101027}},
  volume       = {{25}},
  year         = {{2024}},
}

@article{53212,
  author       = {{Mahmoodi, Ehsan and Fathi, Masood and Tavana, Madjid and Ghobakhloo, Morteza and Ng, Amos H.C.}},
  issn         = {{0278-6125}},
  journal      = {{Journal of Manufacturing Systems}},
  keywords     = {{Industrial and Manufacturing Engineering, Hardware and Architecture, Software, Control and Systems Engineering}},
  pages        = {{287--307}},
  publisher    = {{Elsevier BV}},
  title        = {{{Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing}}},
  doi          = {{10.1016/j.jmsy.2023.11.019}},
  volume       = {{72}},
  year         = {{2024}},
}

@article{46264,
  abstract     = {{System-level interconnects provide the
backbone for increasingly complex systems on a chip. Their
vulnerability to electromigration and crosstalk can lead to
serious reliability and safety issues during the system lifetime.
This article presents an approach for periodic in-system testing
which maintains a reliability profile to detect potential
problems before they actually cause a failure. Relying on a
common infrastructure for EM-aware system workload
management and test, it minimizes the stress induced by the
test itself and contributes to the self-healing of system-induced
electromigration degradations. }},
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  issn         = {{2168-2356}},
  journal      = {{IEEE Design &Test}},
  keywords     = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}},
  pages        = {{1--1}},
  publisher    = {{Institute of Electrical and Electronics Engineers (IEEE)}},
  title        = {{{Workload-Aware Periodic Interconnect BIST}}},
  doi          = {{10.1109/mdat.2023.3298849}},
  year         = {{2023}},
}

@article{53220,
  author       = {{Tavana, Madjid and Khalili Nasr, Arash and Ahmadabadi, Alireza Barati and Amiri, Alireza Shamekhi and Mina, Hassan}},
  issn         = {{2542-6605}},
  journal      = {{Internet of Things}},
  keywords     = {{Management of Technology and Innovation, Artificial Intelligence, Computer Science Applications, Hardware and Architecture, Engineering (miscellaneous), Information Systems, Computer Science (miscellaneous), Software}},
  publisher    = {{Elsevier BV}},
  title        = {{{An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks}}},
  doi          = {{10.1016/j.iot.2023.100786}},
  volume       = {{22}},
  year         = {{2023}},
}

@article{45361,
  abstract     = {{<jats:p> The non-orthogonal local submatrix method applied to electronic structure–based molecular dynamics simulations is shown to exceed 1.1 EFLOP/s in FP16/FP32-mixed floating-point arithmetic when using 4400 NVIDIA A100 GPUs of the Perlmutter system. This is enabled by a modification of the original method that pushes the sustained fraction of the peak performance to about 80%. Example calculations are performed for SARS-CoV-2 spike proteins with up to 83 million atoms. </jats:p>}},
  author       = {{Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Kühne, Thomas and Plessl, Christian}},
  issn         = {{1094-3420}},
  journal      = {{The International Journal of High Performance Computing Applications}},
  keywords     = {{Hardware and Architecture, Theoretical Computer Science, Software}},
  publisher    = {{SAGE Publications}},
  title        = {{{Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics}}},
  doi          = {{10.1177/10943420231177631}},
  year         = {{2023}},
}

@phdthesis{29769,
  abstract     = {{Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.}},
  author       = {{Ahmed, Qazi Arbab}},
  keywords     = {{FPGA Security, Hardware Trojans, Bitstream-level Trojans, Bitstream Verification}},
  publisher    = {{ Paderborn University, Paderborn, Germany}},
  title        = {{{Hardware Trojans in Reconfigurable Computing}}},
  doi          = {{10.17619/UNIPB/1-1271}},
  year         = {{2022}},
}

@article{45847,
  abstract     = {{<jats:title>Abstract</jats:title>
               <jats:p>In this paper, we investigate the parameterized complexity of model checking for Dependence and Independence logic, which are well studied logics in the area of Team Semantics. We start with a list of nine immediate parameterizations for this problem, namely the number of disjunctions (i.e. splits)/(free) variables/universal quantifiers, formula-size, the tree-width of the Gaifman graph of the input structure, the size of the universe/team and the arity of dependence atoms. We present a comprehensive picture of the parameterized complexity of model checking and obtain a division of the problem into tractable and various intractable degrees. Furthermore, we also consider the complexity of the most important variants (data and expression complexity) of the model checking problem by fixing parts of the input.</jats:p>}},
  author       = {{Kontinen, Juha and Meier, Arne and Mahmood, Yasir}},
  issn         = {{0955-792X}},
  journal      = {{Journal of Logic and Computation}},
  keywords     = {{Logic, Hardware and Architecture, Arts and Humanities (miscellaneous), Software, Theoretical Computer Science}},
  number       = {{8}},
  pages        = {{1624--1644}},
  publisher    = {{Oxford University Press (OUP)}},
  title        = {{{A parameterized view on the complexity of dependence and independence logic}}},
  doi          = {{10.1093/logcom/exac070}},
  volume       = {{32}},
  year         = {{2022}},
}

@article{33684,
  author       = {{Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Schütt, Ole and Lazzaro, Alfio and Pabst, Hans and Mohr, Stephan and Hutter, Jürg and Kühne, Thomas and Plessl, Christian}},
  issn         = {{0167-8191}},
  journal      = {{Parallel Computing}},
  keywords     = {{Artificial Intelligence, Computer Graphics and Computer-Aided Design, Computer Networks and Communications, Hardware and Architecture, Theoretical Computer Science, Software}},
  publisher    = {{Elsevier BV}},
  title        = {{{Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms}}},
  doi          = {{10.1016/j.parco.2022.102920}},
  volume       = {{111}},
  year         = {{2022}},
}

@phdthesis{26746,
  abstract     = {{Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts.

This thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques.}},
  author       = {{Wiersema, Tobias}},
  keywords     = {{Proof-Carrying Hardware, Formal Verification, Sequential Circuits, Non-Functional Properties, Functional Properties}},
  pages        = {{293}},
  publisher    = {{Paderborn University}},
  title        = {{{Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}}},
  year         = {{2021}},
}

@article{30907,
  author       = {{Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}},
  issn         = {{0018-9340}},
  journal      = {{IEEE Transactions on Computers}},
  keywords     = {{Computational Theory and Mathematics, Hardware and Architecture, Theoretical Computer Science, Software}},
  pages        = {{1--1}},
  publisher    = {{Institute of Electrical and Electronics Engineers (IEEE)}},
  title        = {{{Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}}},
  doi          = {{10.1109/tc.2021.3107196}},
  year         = {{2021}},
}

@article{45844,
  abstract     = {{<jats:title>Abstract</jats:title>
               <jats:p>Abductive reasoning is a non-monotonic formalism stemming from the work of Peirce. It describes the process of deriving the most plausible explanations of known facts. Considering the positive version, asking for sets of variables as explanations, we study, besides the problem of wether there exists a set of explanations, two explanation size limited variants of this reasoning problem (less than or equal to, and equal to a given size bound). In this paper, we present a thorough two-dimensional classification of these problems: the first dimension is regarding the parameterized complexity under a wealth of different parameterizations, and the second dimension spans through all possible Boolean fragments of these problems in Schaefer’s constraint satisfaction framework with co-clones (T. J. Schaefer. The complexity of satisfiability problems. In Proceedings of the 10th Annual ACM Symposium on Theory of Computing, May 1–3, 1978, San Diego, California, USA, R.J. Lipton, W.A. Burkhard, W.J. Savitch, E.P. Friedman, A.V. Aho eds, pp. 216–226. ACM, 1978). Thereby, we almost complete the parameterized complexity classification program initiated by Fellows et al. (The parameterized complexity of abduction. In Proceedings of the Twenty-Sixth AAAI Conference on Articial Intelligence, July 22–26, 2012, Toronto, Ontario, Canada, J. Homann, B. Selman eds. AAAI Press, 2012), partially building on the results by Nordh and Zanuttini (What makes propositional abduction tractable. Artificial Intelligence, 172, 1245–1284, 2008). In this process, we outline a fine-grained analysis of the inherent parameterized intractability of these problems and pinpoint their FPT parts. As the standard algebraic approach is not applicable to our problems, we develop an alternative method that makes the algebraic tools partially available again.</jats:p>}},
  author       = {{Mahmood, Yasir and Meier, Arne and Schmidt, Johannes}},
  issn         = {{0955-792X}},
  journal      = {{Journal of Logic and Computation}},
  keywords     = {{Logic, Hardware and Architecture, Arts and Humanities (miscellaneous), Software, Theoretical Computer Science}},
  number       = {{1}},
  pages        = {{266--296}},
  publisher    = {{Oxford University Press (OUP)}},
  title        = {{{Parameterized complexity of abduction in Schaefer’s framework}}},
  doi          = {{10.1093/logcom/exaa079}},
  volume       = {{31}},
  year         = {{2021}},
}

@article{27841,
  abstract     = {{Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.}},
  author       = {{Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}},
  journal      = {{IEEE Access}},
  keywords     = {{Software Analysis, Abstract Interpretation, Custom Instruction, Hardware Verification}},
  publisher    = {{IEEE}},
  title        = {{{Software/Hardware Co-Verification for Custom Instruction Set Processors}}},
  doi          = {{10.1109/ACCESS.2021.3131213}},
  year         = {{2021}},
}

@article{17358,
  abstract     = {{Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.}},
  author       = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}},
  issn         = {{1557-9999}},
  journal      = {{IEEE Transactions On Very Large Scale Integration Systems}},
  keywords     = {{Approximate circuit synthesis, approximate computing, error metrics, formal verification, proof-carrying hardware}},
  number       = {{9}},
  pages        = {{2084 -- 2088}},
  publisher    = {{IEEE}},
  title        = {{{Proof-carrying Approximate Circuits}}},
  doi          = {{10.1109/TVLSI.2020.3008061}},
  volume       = {{28}},
  year         = {{2020}},
}

@misc{1097,
  author       = {{Jentzsch, Felix Paul}},
  keywords     = {{Approximate Computing, Proof-Carrying Hardware, Formal Verification}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Enforcing IP Core Connection Properties with Verifiable Security Monitors}}},
  year         = {{2018}},
}

@inproceedings{10676,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2017 International Conference on Field Programmable Technology (ICFPT)}},
  keywords     = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}},
  pages        = {{215--218}},
  title        = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}},
  doi          = {{10.1109/FPT.2017.8280144}},
  year         = {{2017}},
}

@inproceedings{10780,
  author       = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}},
  booktitle    = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}},
  keywords     = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}},
  pages        = {{1--8}},
  title        = {{{Computational self-awareness as design approach for visual sensor nodes}}},
  doi          = {{10.1109/ReCoSoC.2017.8016147}},
  year         = {{2017}},
}

@inproceedings{15873,
  author       = {{Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}},
  booktitle    = {{2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}},
  isbn         = {{9781467394062}},
  keywords     = {{Electromyography, Feature extraction, Delays, Hardware  Pattern recognition, Prosthetics, High definition video}},
  location     = {{Mexiko City, Mexiko}},
  publisher    = {{IEEE}},
  title        = {{{FPGA-based acceleration of high density myoelectric signal processing}}},
  doi          = {{10.1109/reconfig.2015.7393312}},
  year         = {{2016}},
}

@inproceedings{10779,
  author       = {{Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}},
  booktitle    = {{25th International Conference on Field Programmable Logic and Applications (FPL)}},
  issn         = {{1946-147X}},
  keywords     = {{embedded systems, field programmable gate arrays, operating systems (computers), scheduling, μC/OS-II, FPGAs, OS foundation, SafeRTOS, Xenomai, chip utilization ration, complex time constraints, embedded systems, hard real-time hardware task allocation, hard real-time hardware task scheduling, hardware-software real-time operating systems, partially reconfigurable field-programmable gate arrays, resource constraints, safety-critical RTOS, Field programmable gate arrays, Hardware, Job shop scheduling, Real-time systems, Shape, Software}},
  publisher    = {{Imperial College}},
  title        = {{{Over effective hard real-time hardware tasks scheduling and allocation}}},
  doi          = {{10.1109/FPL.2015.7293994}},
  year         = {{2015}},
}

@article{39479,
  author       = {{Vidor, Fábio and Meyers, Thorsten and Hilleringmann, Ulrich}},
  issn         = {{2079-9292}},
  journal      = {{Electronics}},
  keywords     = {{Electrical and Electronic Engineering, Computer Networks and Communications, Hardware and Architecture, Signal Processing, Control and Systems Engineering}},
  number       = {{3}},
  pages        = {{480--506}},
  publisher    = {{MDPI AG}},
  title        = {{{Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors}}},
  doi          = {{10.3390/electronics4030480}},
  volume       = {{4}},
  year         = {{2015}},
}

@inproceedings{10674,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}},
  keywords     = {{Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}},
  pages        = {{1--4}},
  title        = {{{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}},
  doi          = {{10.1109/FPL.2014.6927437}},
  year         = {{2014}},
}