@article{46266, author = {{Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}}, issn = {{0018-9340}}, journal = {{IEEE Transactions on Computers}}, keywords = {{Computational Theory and Mathematics, Hardware and Architecture, Theoretical Computer Science, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}}}, doi = {{10.1109/tc.2014.2329687}}, year = {{2014}}, } @inproceedings{10620, author = {{Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}}, booktitle = {{Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}}, keywords = {{fault tolerant computing, field programmable gate arrays, logic design, reliability, BYU-LANL tool, DRM tool flow, FPGA based hardware designs, avionic application, device technologies, dynamic reliability management, fault-tolerant operation, hardware designs, reconfiguring reliability levels, space applications, Field programmable gate arrays, Hardware, Redundancy, Reliability engineering, Runtime, Tunneling magnetoresistance}}, pages = {{1--6}}, title = {{{Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}}}, doi = {{10.1109/ReConFig.2013.6732280}}, year = {{2013}}, } @inproceedings{36994, abstract = {{This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP.}}, author = {{Xie, Tao and Müller, Wolfgang and Letombe, Florian}}, booktitle = {{Proceedings of SOCC2012}}, keywords = {{Analytical models, Hardware design languages, Microprocessors, Cost function, Data models, Search problems, IP networks}}, publisher = {{IEEE}}, title = {{{Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}}}, doi = {{10.1109/SOCC.2012.6398362}}, year = {{2012}}, } @inproceedings{37002, abstract = {{HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.}}, author = {{Xie, Tao and Müller, Wolfgang and Letombe, Florian}}, booktitle = {{Proceedings of Euromicro DSD 2011}}, isbn = {{978-1-4577-1048-3}}, keywords = {{Hardware design languages, Cost function, Computational modeling, Fault detection, Data models, Analytical models, Testing}}, publisher = {{IEEE}}, title = {{{HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}}}, doi = {{10.1109/DSD.2011.83}}, year = {{2011}}, } @inproceedings{37009, abstract = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}}, author = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Assertion-Based Verification of RTOS Properties}}}, doi = {{10.1109/DATE.2010.5457130}}, year = {{2010}}, } @inproceedings{37011, abstract = {{Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study.}}, author = {{Klobedanz, Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10, Dresden}}, keywords = {{Timing, Programming, Automotive engineering, Application software, Hardware, Computer architecture, Communication system software, Software architecture, Delay, Software standards}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study}}}, doi = {{10.1109/DATE.2010.5457125}}, year = {{2010}}, } @inproceedings{37040, abstract = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}}, author = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}}, doi = {{10.1109/DATE.2010.5456965}}, year = {{2010}}, } @inproceedings{37053, abstract = {{Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.}}, author = {{Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}}, booktitle = {{Proceedings of HLDVT2010}}, keywords = {{Hardware, Microprogramming, Application software, Timing, Protocols, Virtual prototyping, Real time systems, Sampling methods, Operating systems, Emulation}}, location = {{Anaheim, FL, USA}}, publisher = {{IEEE}}, title = {{{Verification of Real-Time Properties for Hardware-Dependant Software}}}, year = {{2010}}, } @inproceedings{37039, abstract = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}}, author = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}}, doi = {{10.1109/DATE.2010.5456965}}, year = {{2010}}, } @inbook{33814, abstract = {{Rapidly rising system complexity has created a growing productivity gap in the design of electronic systems. One critical component is Hardware-dependent Software (HdS), the importance of which is often underestimated. In this chap- ter, we introduce HdS and illustrate its role in the overall system design context. We also provide a brief overview and define a basic HdS terminology and con- clude with a brief outlook over the following chapters in this book.}}, author = {{Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}}, booktitle = {{Hardware Dependent Software - Principles and Practice}}, editor = {{Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}}, isbn = {{978-1-4020-9435-4}}, keywords = {{Hardware-dependent Software, Systems Complexity, Productivity Gap}}, pages = {{1--14}}, publisher = {{Springer Verlag}}, title = {{{Hardware-dependent Software - Introduction and Overview}}}, doi = {{10.1007/978-1-4020-9436-1_1}}, year = {{2009}}, } @inproceedings{2262, abstract = {{In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. }}, author = {{Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}}, keywords = {{EvoCache, evolvable hardware, computer architecture}}, pages = {{11--18}}, publisher = {{IEEE Computer Society}}, title = {{{EvoCaches: Application-specific Adaptation of Cache Mapping}}}, year = {{2009}}, } @inproceedings{6508, abstract = {{In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.}}, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}}, isbn = {{076952866X}}, keywords = {{integrated circuit design, hardware evolution, evolutionary hardware design, evolutionary optimizers, hash functions, preengineered circuits, Hardware, Circuits, Design optimization, Visualization, Genetic programming, Genetic mutations, Clustering algorithms, Biological cells, Field programmable gate arrays, Routing}}, location = {{Edinburgh, UK}}, pages = {{447--454}}, publisher = {{IEEE}}, title = {{{MOVES: A Modular Framework for Hardware Evolution}}}, doi = {{10.1109/ahs.2007.73}}, year = {{2007}}, } @article{10646, author = {{Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}}, issn = {{1751-8601}}, journal = {{IET Computers Digital Techniques}}, keywords = {{reconfigurable architectures, resource allocation, device reconfiguration time, dynamic hardware reconfiguration, dynamically reconfigurable hardware, light-weight runtime system, merge server distribute load, periodic real-time tasks, runtime system overheads, schedulability analysis, scheduling technique, server-based execution, synthesis tool flow}}, number = {{4}}, pages = {{295--302}}, title = {{{Server-based execution of periodic tasks on dynamically reconfigurable hardware}}}, doi = {{10.1049/iet-cdt:20060186}}, volume = {{1}}, year = {{2007}}, } @inproceedings{38107, abstract = {{TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML.}}, author = {{Großmann, Jürgen and Müller, Wolfgang}}, booktitle = {{Proc. of ISOLA 06}}, isbn = {{978-0-7695-3071-0}}, keywords = {{System testing, Software testing, Automotive engineering, Automatic testing, Machinery production industries, Protocols, Hardware design languages, Samarium, XML, Computer industry}}, location = {{Paphos, Cyprus}}, title = {{{A Formal Behavioral Semantics for TestML}}}, doi = {{10.1109/ISoLA.2006.37}}, year = {{2006}}, } @inproceedings{39029, abstract = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}}, booktitle = {{Proceedings of DATE’05}}, isbn = {{0-7695-2288-2}}, keywords = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}}, publisher = {{IEEE}}, title = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}}, doi = {{10.1109/DATE.2005.20}}, year = {{2005}}, } @inproceedings{39030, abstract = {{StateCharts are well accepted for embedded systems specification for various applications. However, for the specification of complex systems they have several limitations. In this article, we present a novel approach to efficiently execute an UML 2.0 subset for embedded real- time systems implementation with focus on hardware interrupts, software exceptions, and timeouts. We introduce a UML Virtual Machine, which directly executes sequence diagrams, which are embedded into hierarchically structured state transition diagrams. Whereas state diagrams are directly executed as Embedded State Machines (ESMs), sequence diagrams are translated into UVM Bytecode. The final UVM execution is performed by the interaction of the ESM and the Bytecode Interpreter. Due to our completely model- based approach, the UVM runtime kernel is easily adaptable and scalable to different scheduling and memory management strategies.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of ISNG 05}}, keywords = {{UML, Executable Models, Hardware/Software Co-design, Virtual Machine, Embedded Systems}}, title = {{{A UML Virtual Machine for Embedded Systems}}}, year = {{2005}}, } @inproceedings{39032, abstract = {{Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of VL/HCC 05}}, isbn = {{0-7695-2443-5}}, keywords = {{Unified modeling language, Software design, Virtual machining, Embedded system, Programming, Documentation, Hardware, Computer languages, Operating systems, Runtime}}, title = {{{Transformation of UML State Machines for Direct Execution}}}, doi = {{10.1109/VLHCC.2005.64}}, year = {{2005}}, } @inproceedings{2415, abstract = {{In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, keywords = {{hardware virtualization}}, pages = {{63--69}}, publisher = {{CSREA Press}}, title = {{{Virtualization of Hardware – Introduction and Survey}}}, year = {{2004}}, } @article{39925, author = {{Goser, K. and Hilleringmann, Ulrich and Rueckert, U. and Schumacher, K.}}, issn = {{0272-1732}}, journal = {{IEEE Micro}}, keywords = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}}, number = {{6}}, pages = {{28--44}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{VLSI technologies for artificial neural networks}}}, doi = {{10.1109/40.42985}}, volume = {{9}}, year = {{2002}}, } @article{39926, author = {{Goser, K. and Hilleringmann, Ulrich and Rueckert, U. and Schumacher, K.}}, issn = {{0272-1732}}, journal = {{IEEE Micro}}, keywords = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}}, number = {{6}}, pages = {{28--44}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{VLSI technologies for artificial neural networks}}}, doi = {{10.1109/40.42985}}, volume = {{9}}, year = {{2002}}, }