[{"department":[{"_id":"277"}],"user_id":"51811","_id":"53213","language":[{"iso":"eng"}],"keyword":["Management of Technology and Innovation","Artificial Intelligence","Computer Science Applications","Hardware and Architecture","Engineering (miscellaneous)","Information Systems","Computer Science (miscellaneous)","Software"],"article_number":"101027","publication":"Internet of Things","type":"journal_article","status":"public","volume":25,"date_created":"2024-04-04T13:34:26Z","author":[{"full_name":"Amiri, Arman","last_name":"Amiri","first_name":"Arman"},{"first_name":"Madjid","id":"31858","full_name":"Tavana, Madjid","last_name":"Tavana"},{"last_name":"Arman","full_name":"Arman, Hosein","first_name":"Hosein"}],"date_updated":"2024-04-15T13:08:17Z","publisher":"Elsevier BV","doi":"10.1016/j.iot.2023.101027","title":"An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction","publication_identifier":{"issn":["2542-6605"]},"publication_status":"published","intvolume":"        25","citation":{"apa":"Amiri, A., Tavana, M., &#38; Arman, H. (2024). An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction. <i>Internet of Things</i>, <i>25</i>, Article 101027. <a href=\"https://doi.org/10.1016/j.iot.2023.101027\">https://doi.org/10.1016/j.iot.2023.101027</a>","short":"A. Amiri, M. Tavana, H. Arman, Internet of Things 25 (2024).","mla":"Amiri, Arman, et al. “An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction.” <i>Internet of Things</i>, vol. 25, 101027, Elsevier BV, 2024, doi:<a href=\"https://doi.org/10.1016/j.iot.2023.101027\">10.1016/j.iot.2023.101027</a>.","bibtex":"@article{Amiri_Tavana_Arman_2024, title={An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction}, volume={25}, DOI={<a href=\"https://doi.org/10.1016/j.iot.2023.101027\">10.1016/j.iot.2023.101027</a>}, number={101027}, journal={Internet of Things}, publisher={Elsevier BV}, author={Amiri, Arman and Tavana, Madjid and Arman, Hosein}, year={2024} }","chicago":"Amiri, Arman, Madjid Tavana, and Hosein Arman. “An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction.” <i>Internet of Things</i> 25 (2024). <a href=\"https://doi.org/10.1016/j.iot.2023.101027\">https://doi.org/10.1016/j.iot.2023.101027</a>.","ieee":"A. Amiri, M. Tavana, and H. Arman, “An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction,” <i>Internet of Things</i>, vol. 25, Art. no. 101027, 2024, doi: <a href=\"https://doi.org/10.1016/j.iot.2023.101027\">10.1016/j.iot.2023.101027</a>.","ama":"Amiri A, Tavana M, Arman H. An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction. <i>Internet of Things</i>. 2024;25. doi:<a href=\"https://doi.org/10.1016/j.iot.2023.101027\">10.1016/j.iot.2023.101027</a>"},"year":"2024"},{"status":"public","type":"journal_article","publication":"Journal of Manufacturing Systems","language":[{"iso":"eng"}],"keyword":["Industrial and Manufacturing Engineering","Hardware and Architecture","Software","Control and Systems Engineering"],"user_id":"51811","department":[{"_id":"277"}],"_id":"53212","citation":{"apa":"Mahmoodi, E., Fathi, M., Tavana, M., Ghobakhloo, M., &#38; Ng, A. H. C. (2024). Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing. <i>Journal of Manufacturing Systems</i>, <i>72</i>, 287–307. <a href=\"https://doi.org/10.1016/j.jmsy.2023.11.019\">https://doi.org/10.1016/j.jmsy.2023.11.019</a>","mla":"Mahmoodi, Ehsan, et al. “Data-Driven Simulation-Based Decision Support System for Resource Allocation in Industry 4.0 and Smart Manufacturing.” <i>Journal of Manufacturing Systems</i>, vol. 72, Elsevier BV, 2024, pp. 287–307, doi:<a href=\"https://doi.org/10.1016/j.jmsy.2023.11.019\">10.1016/j.jmsy.2023.11.019</a>.","bibtex":"@article{Mahmoodi_Fathi_Tavana_Ghobakhloo_Ng_2024, title={Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing}, volume={72}, DOI={<a href=\"https://doi.org/10.1016/j.jmsy.2023.11.019\">10.1016/j.jmsy.2023.11.019</a>}, journal={Journal of Manufacturing Systems}, publisher={Elsevier BV}, author={Mahmoodi, Ehsan and Fathi, Masood and Tavana, Madjid and Ghobakhloo, Morteza and Ng, Amos H.C.}, year={2024}, pages={287–307} }","short":"E. Mahmoodi, M. Fathi, M. Tavana, M. Ghobakhloo, A.H.C. Ng, Journal of Manufacturing Systems 72 (2024) 287–307.","ama":"Mahmoodi E, Fathi M, Tavana M, Ghobakhloo M, Ng AHC. Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing. <i>Journal of Manufacturing Systems</i>. 2024;72:287-307. doi:<a href=\"https://doi.org/10.1016/j.jmsy.2023.11.019\">10.1016/j.jmsy.2023.11.019</a>","chicago":"Mahmoodi, Ehsan, Masood Fathi, Madjid Tavana, Morteza Ghobakhloo, and Amos H.C. Ng. “Data-Driven Simulation-Based Decision Support System for Resource Allocation in Industry 4.0 and Smart Manufacturing.” <i>Journal of Manufacturing Systems</i> 72 (2024): 287–307. <a href=\"https://doi.org/10.1016/j.jmsy.2023.11.019\">https://doi.org/10.1016/j.jmsy.2023.11.019</a>.","ieee":"E. Mahmoodi, M. Fathi, M. Tavana, M. Ghobakhloo, and A. H. C. Ng, “Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing,” <i>Journal of Manufacturing Systems</i>, vol. 72, pp. 287–307, 2024, doi: <a href=\"https://doi.org/10.1016/j.jmsy.2023.11.019\">10.1016/j.jmsy.2023.11.019</a>."},"page":"287-307","intvolume":"        72","year":"2024","publication_status":"published","publication_identifier":{"issn":["0278-6125"]},"doi":"10.1016/j.jmsy.2023.11.019","title":"Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing","author":[{"last_name":"Mahmoodi","full_name":"Mahmoodi, Ehsan","first_name":"Ehsan"},{"last_name":"Fathi","full_name":"Fathi, Masood","first_name":"Masood"},{"first_name":"Madjid","last_name":"Tavana","full_name":"Tavana, Madjid","id":"31858"},{"last_name":"Ghobakhloo","full_name":"Ghobakhloo, Morteza","first_name":"Morteza"},{"last_name":"Ng","full_name":"Ng, Amos H.C.","first_name":"Amos H.C."}],"date_created":"2024-04-04T13:33:48Z","volume":72,"publisher":"Elsevier BV","date_updated":"2024-04-15T13:08:02Z"},{"page":"1-1","citation":{"apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>","mla":"Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>}, journal={IEEE Design &#38;Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &#38;Test (2023) 1–1.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>. Published online 2023:1-1. doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” <i>IEEE Design &#38;Test</i>, pp. 1–1, 2023, doi: <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, 2023, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>."},"year":"2023","publication_identifier":{"issn":["2168-2356","2168-2364"]},"publication_status":"published","doi":"10.1109/mdat.2023.3298849","main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315"}],"title":"Workload-Aware Periodic Interconnect BIST","date_created":"2023-08-02T11:07:43Z","author":[{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2024-03-22T17:15:10Z","status":"public","abstract":[{"lang":"eng","text":"System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. "}],"publication":"IEEE Design &Test","type":"journal_article","language":[{"iso":"eng"}],"keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"article_type":"original","department":[{"_id":"48"}],"user_id":"209","_id":"46264"},{"_id":"53220","department":[{"_id":"277"}],"user_id":"51811","keyword":["Management of Technology and Innovation","Artificial Intelligence","Computer Science Applications","Hardware and Architecture","Engineering (miscellaneous)","Information Systems","Computer Science (miscellaneous)","Software"],"article_number":"100786","language":[{"iso":"eng"}],"publication":"Internet of Things","type":"journal_article","status":"public","date_updated":"2024-04-15T13:10:41Z","publisher":"Elsevier BV","volume":22,"author":[{"first_name":"Madjid","full_name":"Tavana, Madjid","id":"31858","last_name":"Tavana"},{"last_name":"Khalili Nasr","full_name":"Khalili Nasr, Arash","first_name":"Arash"},{"first_name":"Alireza Barati","last_name":"Ahmadabadi","full_name":"Ahmadabadi, Alireza Barati"},{"first_name":"Alireza Shamekhi","full_name":"Amiri, Alireza Shamekhi","last_name":"Amiri"},{"full_name":"Mina, Hassan","last_name":"Mina","first_name":"Hassan"}],"date_created":"2024-04-04T13:49:53Z","title":"An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks","doi":"10.1016/j.iot.2023.100786","publication_identifier":{"issn":["2542-6605"]},"publication_status":"published","year":"2023","intvolume":"        22","citation":{"ieee":"M. Tavana, A. Khalili Nasr, A. B. Ahmadabadi, A. S. Amiri, and H. Mina, “An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks,” <i>Internet of Things</i>, vol. 22, Art. no. 100786, 2023, doi: <a href=\"https://doi.org/10.1016/j.iot.2023.100786\">10.1016/j.iot.2023.100786</a>.","chicago":"Tavana, Madjid, Arash Khalili Nasr, Alireza Barati Ahmadabadi, Alireza Shamekhi Amiri, and Hassan Mina. “An Interval Multi-Criteria Decision-Making Model for Evaluating Blockchain-IoT Technology in Supply Chain Networks.” <i>Internet of Things</i> 22 (2023). <a href=\"https://doi.org/10.1016/j.iot.2023.100786\">https://doi.org/10.1016/j.iot.2023.100786</a>.","ama":"Tavana M, Khalili Nasr A, Ahmadabadi AB, Amiri AS, Mina H. An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks. <i>Internet of Things</i>. 2023;22. doi:<a href=\"https://doi.org/10.1016/j.iot.2023.100786\">10.1016/j.iot.2023.100786</a>","mla":"Tavana, Madjid, et al. “An Interval Multi-Criteria Decision-Making Model for Evaluating Blockchain-IoT Technology in Supply Chain Networks.” <i>Internet of Things</i>, vol. 22, 100786, Elsevier BV, 2023, doi:<a href=\"https://doi.org/10.1016/j.iot.2023.100786\">10.1016/j.iot.2023.100786</a>.","bibtex":"@article{Tavana_Khalili Nasr_Ahmadabadi_Amiri_Mina_2023, title={An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks}, volume={22}, DOI={<a href=\"https://doi.org/10.1016/j.iot.2023.100786\">10.1016/j.iot.2023.100786</a>}, number={100786}, journal={Internet of Things}, publisher={Elsevier BV}, author={Tavana, Madjid and Khalili Nasr, Arash and Ahmadabadi, Alireza Barati and Amiri, Alireza Shamekhi and Mina, Hassan}, year={2023} }","short":"M. Tavana, A. Khalili Nasr, A.B. Ahmadabadi, A.S. Amiri, H. Mina, Internet of Things 22 (2023).","apa":"Tavana, M., Khalili Nasr, A., Ahmadabadi, A. B., Amiri, A. S., &#38; Mina, H. (2023). An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks. <i>Internet of Things</i>, <i>22</i>, Article 100786. <a href=\"https://doi.org/10.1016/j.iot.2023.100786\">https://doi.org/10.1016/j.iot.2023.100786</a>"}},{"quality_controlled":"1","year":"2023","publisher":"SAGE Publications","date_created":"2023-05-30T09:19:09Z","title":"Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics","publication":"The International Journal of High Performance Computing Applications","abstract":[{"text":"<jats:p> The non-orthogonal local submatrix method applied to electronic structure–based molecular dynamics simulations is shown to exceed 1.1 EFLOP/s in FP16/FP32-mixed floating-point arithmetic when using 4400 NVIDIA A100 GPUs of the Perlmutter system. This is enabled by a modification of the original method that pushes the sustained fraction of the peak performance to about 80%. Example calculations are performed for SARS-CoV-2 spike proteins with up to 83 million atoms. </jats:p>","lang":"eng"}],"keyword":["Hardware and Architecture","Theoretical Computer Science","Software"],"language":[{"iso":"eng"}],"publication_status":"published","publication_identifier":{"issn":["1094-3420","1741-2846"]},"citation":{"chicago":"Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Thomas Kühne, and Christian Plessl. “Breaking the Exascale Barrier for the Electronic Structure Problem in Ab-Initio Molecular Dynamics.” <i>The International Journal of High Performance Computing Applications</i>, 2023. <a href=\"https://doi.org/10.1177/10943420231177631\">https://doi.org/10.1177/10943420231177631</a>.","ieee":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, and C. Plessl, “Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics,” <i>The International Journal of High Performance Computing Applications</i>, Art. no. 109434202311776, 2023, doi: <a href=\"https://doi.org/10.1177/10943420231177631\">10.1177/10943420231177631</a>.","ama":"Schade R, Kenter T, Elgabarty H, Lass M, Kühne T, Plessl C. Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics. <i>The International Journal of High Performance Computing Applications</i>. Published online 2023. doi:<a href=\"https://doi.org/10.1177/10943420231177631\">10.1177/10943420231177631</a>","apa":"Schade, R., Kenter, T., Elgabarty, H., Lass, M., Kühne, T., &#38; Plessl, C. (2023). Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics. <i>The International Journal of High Performance Computing Applications</i>, Article 109434202311776. <a href=\"https://doi.org/10.1177/10943420231177631\">https://doi.org/10.1177/10943420231177631</a>","bibtex":"@article{Schade_Kenter_Elgabarty_Lass_Kühne_Plessl_2023, title={Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics}, DOI={<a href=\"https://doi.org/10.1177/10943420231177631\">10.1177/10943420231177631</a>}, number={109434202311776}, journal={The International Journal of High Performance Computing Applications}, publisher={SAGE Publications}, author={Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2023} }","short":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, C. Plessl, The International Journal of High Performance Computing Applications (2023).","mla":"Schade, Robert, et al. “Breaking the Exascale Barrier for the Electronic Structure Problem in Ab-Initio Molecular Dynamics.” <i>The International Journal of High Performance Computing Applications</i>, 109434202311776, SAGE Publications, 2023, doi:<a href=\"https://doi.org/10.1177/10943420231177631\">10.1177/10943420231177631</a>."},"oa":"1","date_updated":"2023-08-02T15:04:53Z","author":[{"first_name":"Robert","orcid":"0000-0002-6268-539","last_name":"Schade","id":"75963","full_name":"Schade, Robert"},{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Elgabarty","orcid":"0000-0002-4945-1481","full_name":"Elgabarty, Hossam","id":"60250","first_name":"Hossam"},{"first_name":"Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135","full_name":"Lass, Michael"},{"id":"49079","full_name":"Kühne, Thomas","last_name":"Kühne","first_name":"Thomas"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"}],"main_file_link":[{"url":"https://journals.sagepub.com/doi/10.1177/10943420231177631","open_access":"1"}],"doi":"10.1177/10943420231177631","type":"journal_article","status":"public","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"45361","user_id":"75963","department":[{"_id":"27"},{"_id":"518"}],"article_number":"109434202311776","article_type":"original"},{"date_created":"2022-02-07T14:02:36Z","publisher":" Paderborn University, Paderborn, Germany","title":"Hardware Trojans in Reconfigurable Computing","year":"2022","language":[{"iso":"eng"}],"ddc":["004"],"keyword":["FPGA Security","Hardware Trojans","Bitstream-level Trojans","Bitstream Verification"],"abstract":[{"text":"Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.","lang":"eng"},{"text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable systems, the defenders perspective which corresponds to the bitstream-level Trojan detection technique, and the attackers perspective which corresponds to a novel FPGA Trojan attack. From the defender's perspective, we introduce a first-ever successful pre-configuration countermeasure against the ``Malicious LUT''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers perspective, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by bitstream-level verification techniques.","lang":"eng"}],"supervisor":[{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"author":[{"last_name":"Ahmed","orcid":"0000-0002-1837-2254","full_name":"Ahmed, Qazi Arbab","id":"72764","first_name":"Qazi Arbab"}],"oa":"1","date_updated":"2022-11-30T13:39:01Z","main_file_link":[{"open_access":"1","url":"\turn:nbn:de:hbz:466:2-40303"}],"doi":"10.17619/UNIPB/1-1271","publication_status":"published","has_accepted_license":"1","citation":{"apa":"Ahmed, Q. A. (2022). <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany. <a href=\"https://doi.org/10.17619/UNIPB/1-1271\">https://doi.org/10.17619/UNIPB/1-1271</a>","mla":"Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany, 2022, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>.","short":"Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing,  Paderborn University, Paderborn, Germany, Paderborn, 2022.","bibtex":"@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>}, publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab}, year={2022} }","chicago":"Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>. Paderborn:  Paderborn University, Paderborn, Germany, 2022. <a href=\"https://doi.org/10.17619/UNIPB/1-1271\">https://doi.org/10.17619/UNIPB/1-1271</a>.","ieee":"Q. A. Ahmed, <i>Hardware Trojans in Reconfigurable Computing</i>. Paderborn:  Paderborn University, Paderborn, Germany, 2022.","ama":"Ahmed QA. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University, Paderborn, Germany; 2022. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1271\">10.17619/UNIPB/1-1271</a>"},"place":"Paderborn","user_id":"477","department":[{"_id":"78"}],"project":[{"name":"SFB 901: SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"name":"SFB 901 - C2: SFB 901 - Subproject C2","_id":"14"}],"_id":"29769","type":"dissertation","status":"public"},{"user_id":"99353","_id":"45847","extern":"1","type":"journal_article","status":"public","volume":32,"author":[{"last_name":"Kontinen","full_name":"Kontinen, Juha","first_name":"Juha"},{"last_name":"Meier","full_name":"Meier, Arne","first_name":"Arne"},{"last_name":"Mahmood","id":"99353","full_name":"Mahmood, Yasir","first_name":"Yasir"}],"date_updated":"2024-06-04T16:06:37Z","doi":"10.1093/logcom/exac070","publication_identifier":{"issn":["0955-792X","1465-363X"]},"publication_status":"published","page":"1624-1644","intvolume":"        32","citation":{"short":"J. Kontinen, A. Meier, Y. Mahmood, Journal of Logic and Computation 32 (2022) 1624–1644.","bibtex":"@article{Kontinen_Meier_Mahmood_2022, title={A parameterized view on the complexity of dependence and independence logic}, volume={32}, DOI={<a href=\"https://doi.org/10.1093/logcom/exac070\">10.1093/logcom/exac070</a>}, number={8}, journal={Journal of Logic and Computation}, publisher={Oxford University Press (OUP)}, author={Kontinen, Juha and Meier, Arne and Mahmood, Yasir}, year={2022}, pages={1624–1644} }","mla":"Kontinen, Juha, et al. “A Parameterized View on the Complexity of Dependence and Independence Logic.” <i>Journal of Logic and Computation</i>, vol. 32, no. 8, Oxford University Press (OUP), 2022, pp. 1624–44, doi:<a href=\"https://doi.org/10.1093/logcom/exac070\">10.1093/logcom/exac070</a>.","apa":"Kontinen, J., Meier, A., &#38; Mahmood, Y. (2022). A parameterized view on the complexity of dependence and independence logic. <i>Journal of Logic and Computation</i>, <i>32</i>(8), 1624–1644. <a href=\"https://doi.org/10.1093/logcom/exac070\">https://doi.org/10.1093/logcom/exac070</a>","ama":"Kontinen J, Meier A, Mahmood Y. A parameterized view on the complexity of dependence and independence logic. <i>Journal of Logic and Computation</i>. 2022;32(8):1624-1644. doi:<a href=\"https://doi.org/10.1093/logcom/exac070\">10.1093/logcom/exac070</a>","chicago":"Kontinen, Juha, Arne Meier, and Yasir Mahmood. “A Parameterized View on the Complexity of Dependence and Independence Logic.” <i>Journal of Logic and Computation</i> 32, no. 8 (2022): 1624–44. <a href=\"https://doi.org/10.1093/logcom/exac070\">https://doi.org/10.1093/logcom/exac070</a>.","ieee":"J. Kontinen, A. Meier, and Y. Mahmood, “A parameterized view on the complexity of dependence and independence logic,” <i>Journal of Logic and Computation</i>, vol. 32, no. 8, pp. 1624–1644, 2022, doi: <a href=\"https://doi.org/10.1093/logcom/exac070\">10.1093/logcom/exac070</a>."},"language":[{"iso":"eng"}],"keyword":["Logic","Hardware and Architecture","Arts and Humanities (miscellaneous)","Software","Theoretical Computer Science"],"publication":"Journal of Logic and Computation","abstract":[{"lang":"eng","text":"<jats:title>Abstract</jats:title>\r\n               <jats:p>In this paper, we investigate the parameterized complexity of model checking for Dependence and Independence logic, which are well studied logics in the area of Team Semantics. We start with a list of nine immediate parameterizations for this problem, namely the number of disjunctions (i.e. splits)/(free) variables/universal quantifiers, formula-size, the tree-width of the Gaifman graph of the input structure, the size of the universe/team and the arity of dependence atoms. We present a comprehensive picture of the parameterized complexity of model checking and obtain a division of the problem into tractable and various intractable degrees. Furthermore, we also consider the complexity of the most important variants (data and expression complexity) of the model checking problem by fixing parts of the input.</jats:p>"}],"date_created":"2023-07-03T11:36:55Z","publisher":"Oxford University Press (OUP)","title":"A parameterized view on the complexity of dependence and independence logic","issue":"8","year":"2022"},{"language":[{"iso":"eng"}],"keyword":["Artificial Intelligence","Computer Graphics and Computer-Aided Design","Computer Networks and Communications","Hardware and Architecture","Theoretical Computer Science","Software"],"publication":"Parallel Computing","title":"Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms","date_created":"2022-10-11T08:17:02Z","publisher":"Elsevier BV","year":"2022","quality_controlled":"1","article_number":"102920","user_id":"75963","department":[{"_id":"613"},{"_id":"27"},{"_id":"518"}],"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"_id":"33684","status":"public","type":"journal_article","main_file_link":[{"url":"https://www.sciencedirect.com/science/article/pii/S0167819122000242","open_access":"1"}],"doi":"10.1016/j.parco.2022.102920","author":[{"full_name":"Schade, Robert","id":"75963","last_name":"Schade","orcid":"0000-0002-6268-539","first_name":"Robert"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"first_name":"Hossam","full_name":"Elgabarty, Hossam","id":"60250","orcid":"0000-0002-4945-1481","last_name":"Elgabarty"},{"first_name":"Michael","last_name":"Lass","orcid":"0000-0002-5708-7632","id":"24135","full_name":"Lass, Michael"},{"last_name":"Schütt","full_name":"Schütt, Ole","first_name":"Ole"},{"first_name":"Alfio","full_name":"Lazzaro, Alfio","last_name":"Lazzaro"},{"last_name":"Pabst","full_name":"Pabst, Hans","first_name":"Hans"},{"first_name":"Stephan","full_name":"Mohr, Stephan","last_name":"Mohr"},{"last_name":"Hutter","full_name":"Hutter, Jürg","first_name":"Jürg"},{"first_name":"Thomas","id":"49079","full_name":"Kühne, Thomas","last_name":"Kühne"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"volume":111,"oa":"1","date_updated":"2023-08-02T15:03:55Z","citation":{"bibtex":"@article{Schade_Kenter_Elgabarty_Lass_Schütt_Lazzaro_Pabst_Mohr_Hutter_Kühne_et al._2022, title={Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms}, volume={111}, DOI={<a href=\"https://doi.org/10.1016/j.parco.2022.102920\">10.1016/j.parco.2022.102920</a>}, number={102920}, journal={Parallel Computing}, publisher={Elsevier BV}, author={Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Schütt, Ole and Lazzaro, Alfio and Pabst, Hans and Mohr, Stephan and Hutter, Jürg and Kühne, Thomas and et al.}, year={2022} }","mla":"Schade, Robert, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” <i>Parallel Computing</i>, vol. 111, 102920, Elsevier BV, 2022, doi:<a href=\"https://doi.org/10.1016/j.parco.2022.102920\">10.1016/j.parco.2022.102920</a>.","short":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, O. Schütt, A. Lazzaro, H. Pabst, S. Mohr, J. Hutter, T. Kühne, C. Plessl, Parallel Computing 111 (2022).","apa":"Schade, R., Kenter, T., Elgabarty, H., Lass, M., Schütt, O., Lazzaro, A., Pabst, H., Mohr, S., Hutter, J., Kühne, T., &#38; Plessl, C. (2022). Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms. <i>Parallel Computing</i>, <i>111</i>, Article 102920. <a href=\"https://doi.org/10.1016/j.parco.2022.102920\">https://doi.org/10.1016/j.parco.2022.102920</a>","ama":"Schade R, Kenter T, Elgabarty H, et al. Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms. <i>Parallel Computing</i>. 2022;111. doi:<a href=\"https://doi.org/10.1016/j.parco.2022.102920\">10.1016/j.parco.2022.102920</a>","ieee":"R. Schade <i>et al.</i>, “Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms,” <i>Parallel Computing</i>, vol. 111, Art. no. 102920, 2022, doi: <a href=\"https://doi.org/10.1016/j.parco.2022.102920\">10.1016/j.parco.2022.102920</a>.","chicago":"Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Ole Schütt, Alfio Lazzaro, Hans Pabst, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” <i>Parallel Computing</i> 111 (2022). <a href=\"https://doi.org/10.1016/j.parco.2022.102920\">https://doi.org/10.1016/j.parco.2022.102920</a>."},"intvolume":"       111","publication_status":"published","publication_identifier":{"issn":["0167-8191"]}},{"supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"author":[{"id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias"}],"date_updated":"2022-01-06T06:57:26Z","oa":"1","main_file_link":[{"open_access":"1","url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800"}],"publication_status":"published","page":"293","citation":{"ieee":"T. Wiersema, <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn: Paderborn University, 2021.","chicago":"Wiersema, Tobias. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn: Paderborn University, 2021.","ama":"Wiersema T. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn University; 2021.","apa":"Wiersema, T. (2021). <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn University.","short":"T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.","bibtex":"@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2021} }","mla":"Wiersema, Tobias. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware</i>. Paderborn University, 2021."},"place":"Paderborn","department":[{"_id":"78"}],"user_id":"3118","_id":"26746","project":[{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - Subproject B4"}],"type":"dissertation","status":"public","date_created":"2021-10-25T06:35:41Z","publisher":"Paderborn University","title":"Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware","year":"2021","language":[{"iso":"eng"}],"keyword":["Proof-Carrying Hardware","Formal Verification","Sequential Circuits","Non-Functional Properties","Functional Properties"],"ddc":["006"],"abstract":[{"lang":"eng","text":"Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques."},{"lang":"ger","text":"Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen, Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale. Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt werden können."}]},{"date_created":"2022-04-18T10:03:16Z","author":[{"first_name":"Alfonso","full_name":"Rodriguez, Alfonso","last_name":"Rodriguez"},{"first_name":"Andres","full_name":"Otero, Andres","last_name":"Otero"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"first_name":"Eduardo","last_name":"De la Torre","full_name":"De la Torre, Eduardo"}],"date_updated":"2022-04-18T10:04:21Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","doi":"10.1109/tc.2021.3107196","title":"Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs","publication_status":"published","publication_identifier":{"issn":["0018-9340","1557-9956","2326-3814"]},"citation":{"ama":"Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>. Published online 2021:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>","ieee":"A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2021, doi: <a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","chicago":"Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, 2021, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>.","mla":"Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>.","short":"A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1.","bibtex":"@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={<a href=\"https://doi.org/10.1109/tc.2021.3107196\">10.1109/tc.2021.3107196</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }","apa":"Rodriguez, A., Otero, A., Platzner, M., &#38; De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2021.3107196\">https://doi.org/10.1109/tc.2021.3107196</a>"},"page":"1-1","year":"2021","user_id":"398","department":[{"_id":"78"}],"_id":"30907","language":[{"iso":"eng"}],"keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"type":"journal_article","publication":"IEEE Transactions on Computers","status":"public"},{"abstract":[{"lang":"eng","text":"<jats:title>Abstract</jats:title>\r\n               <jats:p>Abductive reasoning is a non-monotonic formalism stemming from the work of Peirce. It describes the process of deriving the most plausible explanations of known facts. Considering the positive version, asking for sets of variables as explanations, we study, besides the problem of wether there exists a set of explanations, two explanation size limited variants of this reasoning problem (less than or equal to, and equal to a given size bound). In this paper, we present a thorough two-dimensional classification of these problems: the first dimension is regarding the parameterized complexity under a wealth of different parameterizations, and the second dimension spans through all possible Boolean fragments of these problems in Schaefer’s constraint satisfaction framework with co-clones (T. J. Schaefer. The complexity of satisfiability problems. In Proceedings of the 10th Annual ACM Symposium on Theory of Computing, May 1–3, 1978, San Diego, California, USA, R.J. Lipton, W.A. Burkhard, W.J. Savitch, E.P. Friedman, A.V. Aho eds, pp. 216–226. ACM, 1978). Thereby, we almost complete the parameterized complexity classification program initiated by Fellows et al. (The parameterized complexity of abduction. In Proceedings of the Twenty-Sixth AAAI Conference on Articial Intelligence, July 22–26, 2012, Toronto, Ontario, Canada, J. Homann, B. Selman eds. AAAI Press, 2012), partially building on the results by Nordh and Zanuttini (What makes propositional abduction tractable. Artificial Intelligence, 172, 1245–1284, 2008). In this process, we outline a fine-grained analysis of the inherent parameterized intractability of these problems and pinpoint their FPT parts. As the standard algebraic approach is not applicable to our problems, we develop an alternative method that makes the algebraic tools partially available again.</jats:p>"}],"publication":"Journal of Logic and Computation","language":[{"iso":"eng"}],"keyword":["Logic","Hardware and Architecture","Arts and Humanities (miscellaneous)","Software","Theoretical Computer Science"],"year":"2021","issue":"1","title":"Parameterized complexity of abduction in Schaefer’s framework","date_created":"2023-07-03T11:35:23Z","publisher":"Oxford University Press (OUP)","status":"public","type":"journal_article","extern":"1","user_id":"99353","department":[{"_id":"574"}],"_id":"45844","citation":{"chicago":"Mahmood, Yasir, Arne Meier, and Johannes Schmidt. “Parameterized Complexity of Abduction in Schaefer’s Framework.” <i>Journal of Logic and Computation</i> 31, no. 1 (2021): 266–96. <a href=\"https://doi.org/10.1093/logcom/exaa079\">https://doi.org/10.1093/logcom/exaa079</a>.","ieee":"Y. Mahmood, A. Meier, and J. Schmidt, “Parameterized complexity of abduction in Schaefer’s framework,” <i>Journal of Logic and Computation</i>, vol. 31, no. 1, pp. 266–296, 2021, doi: <a href=\"https://doi.org/10.1093/logcom/exaa079\">10.1093/logcom/exaa079</a>.","ama":"Mahmood Y, Meier A, Schmidt J. Parameterized complexity of abduction in Schaefer’s framework. <i>Journal of Logic and Computation</i>. 2021;31(1):266-296. doi:<a href=\"https://doi.org/10.1093/logcom/exaa079\">10.1093/logcom/exaa079</a>","bibtex":"@article{Mahmood_Meier_Schmidt_2021, title={Parameterized complexity of abduction in Schaefer’s framework}, volume={31}, DOI={<a href=\"https://doi.org/10.1093/logcom/exaa079\">10.1093/logcom/exaa079</a>}, number={1}, journal={Journal of Logic and Computation}, publisher={Oxford University Press (OUP)}, author={Mahmood, Yasir and Meier, Arne and Schmidt, Johannes}, year={2021}, pages={266–296} }","mla":"Mahmood, Yasir, et al. “Parameterized Complexity of Abduction in Schaefer’s Framework.” <i>Journal of Logic and Computation</i>, vol. 31, no. 1, Oxford University Press (OUP), 2021, pp. 266–96, doi:<a href=\"https://doi.org/10.1093/logcom/exaa079\">10.1093/logcom/exaa079</a>.","short":"Y. Mahmood, A. Meier, J. Schmidt, Journal of Logic and Computation 31 (2021) 266–296.","apa":"Mahmood, Y., Meier, A., &#38; Schmidt, J. (2021). Parameterized complexity of abduction in Schaefer’s framework. <i>Journal of Logic and Computation</i>, <i>31</i>(1), 266–296. <a href=\"https://doi.org/10.1093/logcom/exaa079\">https://doi.org/10.1093/logcom/exaa079</a>"},"intvolume":"        31","page":"266-296","publication_status":"published","publication_identifier":{"issn":["0955-792X","1465-363X"]},"doi":"10.1093/logcom/exaa079","author":[{"first_name":"Yasir","last_name":"Mahmood","full_name":"Mahmood, Yasir"},{"first_name":"Arne","full_name":"Meier, Arne","last_name":"Meier"},{"last_name":"Schmidt","full_name":"Schmidt, Johannes","first_name":"Johannes"}],"volume":31,"date_updated":"2024-06-04T16:03:14Z"},{"quality_controlled":"1","publication_status":"published","year":"2021","citation":{"apa":"Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., &#38; Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. <i>IEEE Access</i>. <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">https://doi.org/10.1109/ACCESS.2021.3131213</a>","bibtex":"@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware Co-Verification for Custom Instruction Set Processors}, DOI={<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>}, journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021} }","mla":"Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” <i>IEEE Access</i>, IEEE, 2021, doi:<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>.","short":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021).","chicago":"Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” <i>IEEE Access</i>, 2021. <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">https://doi.org/10.1109/ACCESS.2021.3131213</a>.","ieee":"M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” <i>IEEE Access</i>, 2021, doi: <a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>.","ama":"Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. <i>IEEE Access</i>. Published online 2021. doi:<a href=\"https://doi.org/10.1109/ACCESS.2021.3131213\">10.1109/ACCESS.2021.3131213</a>"},"publisher":"IEEE","date_updated":"2023-01-18T08:34:50Z","author":[{"full_name":"Jakobs, Marie-Christine","last_name":"Jakobs","first_name":"Marie-Christine"},{"first_name":"Felix","id":"22398","full_name":"Pauck, Felix","last_name":"Pauck"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"id":"573","full_name":"Wehrheim, Heike","last_name":"Wehrheim","first_name":"Heike"},{"first_name":"Tobias","last_name":"Wiersema","id":"3118","full_name":"Wiersema, Tobias"}],"date_created":"2021-11-25T14:12:22Z","title":"Software/Hardware Co-Verification for Custom Instruction Set Processors","doi":"10.1109/ACCESS.2021.3131213","publication":"IEEE Access","type":"journal_article","abstract":[{"text":"Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.","lang":"eng"}],"status":"public","_id":"27841","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area B","_id":"3"},{"name":"SFB 901 - Subproject B4","_id":"12"}],"department":[{"_id":"78"}],"user_id":"22398","keyword":["Software Analysis","Abstract Interpretation","Custom Instruction","Hardware Verification"],"language":[{"iso":"eng"}],"funded_apc":"1"},{"language":[{"iso":"eng"}],"keyword":["Approximate circuit synthesis","approximate computing","error metrics","formal verification","proof-carrying hardware"],"abstract":[{"lang":"eng","text":"Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework."}],"publication":"IEEE Transactions On Very Large Scale Integration Systems","title":"Proof-carrying Approximate Circuits","date_created":"2020-07-06T11:21:30Z","publisher":"IEEE","year":"2020","issue":"9","quality_controlled":"1","funded_apc":"1","article_type":"original","user_id":"49051","department":[{"_id":"78"}],"project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"1","name":"SFB 901"}],"_id":"17358","status":"public","type":"journal_article","doi":"10.1109/TVLSI.2020.3008061","author":[{"first_name":"Linus Matthias","id":"49051","full_name":"Witschen, Linus Matthias","last_name":"Witschen"},{"last_name":"Wiersema","full_name":"Wiersema, Tobias","id":"3118","first_name":"Tobias"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"volume":28,"date_updated":"2022-01-06T06:53:09Z","citation":{"apa":"Witschen, L. M., Wiersema, T., &#38; Platzner, M. (2020). Proof-carrying Approximate Circuits. <i>IEEE Transactions On Very Large Scale Integration Systems</i>, <i>28</i>(9), 2084–2088. <a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">https://doi.org/10.1109/TVLSI.2020.3008061</a>","bibtex":"@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }","short":"L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088.","mla":"Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” <i>IEEE Transactions On Very Large Scale Integration Systems</i>, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>.","ama":"Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. <i>IEEE Transactions On Very Large Scale Integration Systems</i>. 2020;28(9):2084-2088. doi:<a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">10.1109/TVLSI.2020.3008061</a>","chicago":"Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” <i>IEEE Transactions On Very Large Scale Integration Systems</i> 28, no. 9 (2020): 2084–88. <a href=\"https://doi.org/10.1109/TVLSI.2020.3008061\">https://doi.org/10.1109/TVLSI.2020.3008061</a>.","ieee":"L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” <i>IEEE Transactions On Very Large Scale Integration Systems</i>, vol. 28, no. 9, pp. 2084–2088, 2020."},"intvolume":"        28","page":"2084 - 2088","publication_status":"published","publication_identifier":{"eissn":["1557-9999"],"issn":["1063-8210"]}},{"date_updated":"2022-01-06T06:50:54Z","publisher":"Universität Paderborn","supervisor":[{"first_name":"Tobias","id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema"}],"author":[{"full_name":"Jentzsch, Felix Paul","last_name":"Jentzsch","first_name":"Felix Paul"}],"date_created":"2018-01-15T16:48:05Z","title":"Enforcing IP Core Connection Properties with Verifiable Security Monitors","year":"2018","citation":{"ama":"Jentzsch FP. <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn; 2018.","chicago":"Jentzsch, Felix Paul. <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn, 2018.","ieee":"F. P. Jentzsch, <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn, 2018.","short":"F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors, Universität Paderborn, 2018.","bibtex":"@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch, Felix Paul}, year={2018} }","mla":"Jentzsch, Felix Paul. <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn, 2018.","apa":"Jentzsch, F. P. (2018). <i>Enforcing IP Core Connection Properties with Verifiable Security Monitors</i>. Universität Paderborn."},"_id":"1097","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"}],"department":[{"_id":"78"}],"user_id":"477","keyword":["Approximate Computing","Proof-Carrying Hardware","Formal Verification"],"language":[{"iso":"eng"}],"type":"bachelorsthesis","status":"public"},{"citation":{"ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>. ; 2017:215-218. doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 215–18, 2017. <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–218.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }","mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–18, doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i> (pp. 215–218). <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>"},"page":"215-218","year":"2017","doi":"10.1109/FPT.2017.8280144","title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-07-10T11:22:59Z","date_updated":"2022-01-06T06:50:49Z","status":"public","type":"conference","publication":"2017 International Conference on Field Programmable Technology (ICFPT)","language":[{"iso":"eng"}],"keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"user_id":"398","department":[{"_id":"78"}],"_id":"10676"},{"year":"2017","citation":{"apa":"Guettatfi, Z., Hübner, P., Platzner, M., &#38; Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>.","bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 1–8, 2017. <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>.","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8.","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2017:1-8. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>"},"page":"1-8","title":"Computational self-awareness as design approach for visual sensor nodes","doi":"10.1109/ReCoSoC.2017.8016147","date_updated":"2022-01-06T06:50:50Z","author":[{"first_name":"Zakarya","last_name":"Guettatfi","full_name":"Guettatfi, Zakarya"},{"first_name":"Philipp","full_name":"Hübner, Philipp","last_name":"Hübner"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"full_name":"Rinner, Bernhard","last_name":"Rinner","first_name":"Bernhard"}],"date_created":"2019-07-10T12:13:15Z","status":"public","type":"conference","publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"language":[{"iso":"eng"}],"_id":"10780","user_id":"3118","department":[{"_id":"78"}]},{"publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","type":"conference","status":"public","_id":"15873","department":[{"_id":"78"}],"user_id":"49051","keyword":["Electromyography","Feature extraction","Delays","Hardware  Pattern recognition","Prosthetics","High definition video"],"language":[{"iso":"eng"}],"publication_identifier":{"isbn":["9781467394062"]},"publication_status":"published","year":"2016","citation":{"ama":"Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2016. doi:<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>","ieee":"A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, Mexiko City, Mexiko, 2016.","chicago":"Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE, 2016. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>.","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","short":"A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2016, doi:<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>.","apa":"Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., &#38; Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. Mexiko City, Mexiko: IEEE. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>"},"date_updated":"2022-01-06T06:52:38Z","publisher":"IEEE","author":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Linus Matthias","id":"49051","full_name":"Witschen, Linus Matthias","last_name":"Witschen"},{"full_name":"Thombansen, Georg","last_name":"Thombansen","first_name":"Georg"},{"last_name":"Kraus","full_name":"Kraus, Florian","first_name":"Florian"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2020-02-11T07:48:56Z","title":"FPGA-based acceleration of high density myoelectric signal processing","doi":"10.1109/reconfig.2015.7393312","conference":{"location":"Mexiko City, Mexiko","name":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)"}},{"publisher":"Imperial College","date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:11:36Z","author":[{"full_name":"Guettatfi, Zakarya","last_name":"Guettatfi","first_name":"Zakarya"},{"first_name":"Omar","full_name":"Kermia, Omar","last_name":"Kermia"},{"last_name":"Khouas","full_name":"Khouas, Abdelhakim","first_name":"Abdelhakim"}],"title":"Over effective hard real-time hardware tasks scheduling and allocation","doi":"10.1109/FPL.2015.7293994","publication_identifier":{"issn":["1946-147X"]},"year":"2015","citation":{"chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College, 2015. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>.","ieee":"Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2015.","ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College; 2015. doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, Imperial College, 2015, doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>.","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }","short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","apa":"Guettatfi, Z., Kermia, O., &#38; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>"},"_id":"10779","department":[{"_id":"78"}],"user_id":"398","keyword":["embedded systems","field programmable gate arrays","operating systems (computers)","scheduling","μC/OS-II","FPGAs","OS foundation","SafeRTOS","Xenomai","chip utilization ration","complex time constraints","embedded systems","hard real-time hardware task allocation","hard real-time hardware task scheduling","hardware-software real-time operating systems","partially reconfigurable field-programmable gate arrays","resource constraints","safety-critical RTOS","Field programmable gate arrays","Hardware","Job shop scheduling","Real-time systems","Shape","Software"],"extern":"1","language":[{"iso":"eng"}],"publication":"25th International Conference on Field Programmable Logic and Applications (FPL)","type":"conference","status":"public"},{"date_updated":"2023-03-21T10:16:23Z","publisher":"MDPI AG","date_created":"2023-01-24T11:23:57Z","author":[{"first_name":"Fábio","last_name":"Vidor","full_name":"Vidor, Fábio"},{"first_name":"Thorsten","last_name":"Meyers","full_name":"Meyers, Thorsten"},{"last_name":"Hilleringmann","full_name":"Hilleringmann, Ulrich","id":"20179","first_name":"Ulrich"}],"volume":4,"title":"Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors","doi":"10.3390/electronics4030480","publication_status":"published","publication_identifier":{"issn":["2079-9292"]},"issue":"3","year":"2015","citation":{"apa":"Vidor, F., Meyers, T., &#38; Hilleringmann, U. (2015). Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors. <i>Electronics</i>, <i>4</i>(3), 480–506. <a href=\"https://doi.org/10.3390/electronics4030480\">https://doi.org/10.3390/electronics4030480</a>","short":"F. Vidor, T. Meyers, U. Hilleringmann, Electronics 4 (2015) 480–506.","bibtex":"@article{Vidor_Meyers_Hilleringmann_2015, title={Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors}, volume={4}, DOI={<a href=\"https://doi.org/10.3390/electronics4030480\">10.3390/electronics4030480</a>}, number={3}, journal={Electronics}, publisher={MDPI AG}, author={Vidor, Fábio and Meyers, Thorsten and Hilleringmann, Ulrich}, year={2015}, pages={480–506} }","mla":"Vidor, Fábio, et al. “Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors.” <i>Electronics</i>, vol. 4, no. 3, MDPI AG, 2015, pp. 480–506, doi:<a href=\"https://doi.org/10.3390/electronics4030480\">10.3390/electronics4030480</a>.","ieee":"F. Vidor, T. Meyers, and U. Hilleringmann, “Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors,” <i>Electronics</i>, vol. 4, no. 3, pp. 480–506, 2015, doi: <a href=\"https://doi.org/10.3390/electronics4030480\">10.3390/electronics4030480</a>.","chicago":"Vidor, Fábio, Thorsten Meyers, and Ulrich Hilleringmann. “Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors.” <i>Electronics</i> 4, no. 3 (2015): 480–506. <a href=\"https://doi.org/10.3390/electronics4030480\">https://doi.org/10.3390/electronics4030480</a>.","ama":"Vidor F, Meyers T, Hilleringmann U. Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors. <i>Electronics</i>. 2015;4(3):480-506. doi:<a href=\"https://doi.org/10.3390/electronics4030480\">10.3390/electronics4030480</a>"},"page":"480-506","intvolume":"         4","_id":"39479","user_id":"20179","department":[{"_id":"59"}],"keyword":["Electrical and Electronic Engineering","Computer Networks and Communications","Hardware and Architecture","Signal Processing","Control and Systems Engineering"],"language":[{"iso":"eng"}],"type":"journal_article","publication":"Electronics","status":"public"},{"year":"2014","citation":{"short":"N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4, doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i> (pp. 1–4). <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>","ama":"Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>. ; 2014:1-4. doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 1–4, 2014. <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4."},"page":"1-4","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:18:01Z","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"title":"A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms","doi":"10.1109/FPL.2014.6927437","type":"conference","publication":"24th Intl. Conf. on Field Programmable Logic and Applications (FPL)","status":"public","project":[{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"_id":"10674","user_id":"3118","department":[{"_id":"78"}],"keyword":["Linux","hardware-software codesign","multiprocessing systems","parallel processing","LEON3 multicore platform","Linux kernel","PMU","hardware counters","hardware-software infrastructure","high performance embedded computing","perf_event","performance monitoring unit","Computer architecture","Hardware","Monitoring","Phasor measurement units","Radiation detectors","Registers","Software"],"language":[{"iso":"eng"}]}]