[{"_id":"46266","department":[{"_id":"48"}],"user_id":"78614","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"extern":"1","language":[{"iso":"eng"}],"publication":"IEEE Transactions on Computers","type":"journal_article","status":"public","date_updated":"2023-08-02T11:32:37Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","author":[{"first_name":"Bijan","full_name":"Alizadeh, Bijan","last_name":"Alizadeh"},{"full_name":"Behnam, Payman","last_name":"Behnam","first_name":"Payman"},{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610"}],"date_created":"2023-08-02T11:15:22Z","title":"A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs","doi":"10.1109/tc.2014.2329687","publication_identifier":{"issn":["0018-9340"]},"publication_status":"published","year":"2014","page":"1-1","citation":{"bibtex":"@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}, DOI={<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }","mla":"Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2014, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>.","short":"B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.","apa":"Alizadeh, B., Behnam, P., &#38; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>","ama":"Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>. Published online 2014:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>","chicago":"Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” <i>IEEE Transactions on Computers</i>, 2014, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>.","ieee":"B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2014, doi: <a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>."}},{"doi":"10.1109/ReConFig.2013.6732280","title":"Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime","date_created":"2019-07-10T09:32:57Z","author":[{"last_name":"Anwer","full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb"},{"first_name":"Sebastian","full_name":"Meisner, Sebastian","last_name":"Meisner"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:48Z","page":"1-6","citation":{"mla":"Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 2013, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>.","bibtex":"@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013}, pages={1–6} }","short":"J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.","apa":"Anwer, J., Meisner, S., &#38; Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i> (pp. 1–6). <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>","chicago":"Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 1–6, 2013. <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>.","ieee":"J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime,” in <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i>, 2013, pp. 1–6.","ama":"Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>. ; 2013:1-6. doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>"},"year":"2013","language":[{"iso":"eng"}],"keyword":["fault tolerant computing","field programmable gate arrays","logic design","reliability","BYU-LANL tool","DRM tool flow","FPGA based hardware designs","avionic application","device technologies","dynamic reliability management","fault-tolerant operation","hardware designs","reconfiguring reliability levels","space applications","Field programmable gate arrays","Hardware","Redundancy","Reliability engineering","Runtime","Tunneling magnetoresistance"],"department":[{"_id":"78"}],"user_id":"3118","_id":"10620","status":"public","publication":"Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on","type":"conference"},{"date_updated":"2023-01-17T08:46:29Z","publisher":"IEEE","author":[{"first_name":"Tao ","last_name":"Xie","full_name":"Xie, Tao "},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Florian","last_name":"Letombe","full_name":"Letombe, Florian"}],"date_created":"2023-01-17T08:46:14Z","title":"Mutation-Analysis Driven Functional Verification of a Soft Microprocessor","doi":"10.1109/SOCC.2012.6398362","publication_identifier":{"eisbn":["978-1-4673-1295-0"]},"place":" Niagara Falls, NY, USA ","year":"2012","citation":{"apa":"Xie, T., Müller, W., &#38; Letombe, F. (2012). Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. <i>Proceedings of SOCC2012</i>. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>","bibtex":"@inproceedings{Xie_Müller_Letombe_2012, place={ Niagara Falls, NY, USA }, title={Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}, DOI={<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>}, booktitle={Proceedings of SOCC2012}, publisher={IEEE}, author={Xie, Tao  and Müller, Wolfgang and Letombe, Florian}, year={2012} }","mla":"Xie, Tao, et al. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” <i>Proceedings of SOCC2012</i>, IEEE, 2012, doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","short":"T. Xie, W. Müller, F. Letombe, in: Proceedings of SOCC2012, IEEE,  Niagara Falls, NY, USA , 2012.","ieee":"T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor,” 2012, doi: <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","chicago":"Xie, Tao , Wolfgang Müller, and Florian Letombe. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” In <i>Proceedings of SOCC2012</i>.  Niagara Falls, NY, USA : IEEE, 2012. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>.","ama":"Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. In: <i>Proceedings of SOCC2012</i>. IEEE; 2012. doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>"},"_id":"36994","user_id":"5786","department":[{"_id":"672"}],"keyword":["Analytical models","Hardware design languages","Microprocessors","Cost function","Data models","Search problems","IP networks"],"language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of SOCC2012","abstract":[{"lang":"eng","text":"This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP."}],"status":"public"},{"publication_identifier":{"isbn":["978-1-4577-1048-3"]},"place":"Oulu, Finnland","year":"2011","citation":{"ieee":"T. Xie, W. Müller, and F. Letombe, “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search,” 2011, doi: <a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>.","chicago":"Xie, Tao, Wolfgang Müller, and Florian Letombe. “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.” In <i>Proceedings of Euromicro DSD 2011</i>. Oulu, Finnland: IEEE, 2011. <a href=\"https://doi.org/10.1109/DSD.2011.83\">https://doi.org/10.1109/DSD.2011.83</a>.","ama":"Xie T, Müller W, Letombe F. HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. In: <i>Proceedings of Euromicro DSD 2011</i>. IEEE; 2011. doi:<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>","bibtex":"@inproceedings{Xie_Müller_Letombe_2011, place={Oulu, Finnland}, title={HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}, DOI={<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>}, booktitle={Proceedings of Euromicro DSD 2011}, publisher={IEEE}, author={Xie, Tao and Müller, Wolfgang and Letombe, Florian}, year={2011} }","mla":"Xie, Tao, et al. “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.” <i>Proceedings of Euromicro DSD 2011</i>, IEEE, 2011, doi:<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>.","short":"T. Xie, W. Müller, F. Letombe, in: Proceedings of Euromicro DSD 2011, IEEE, Oulu, Finnland, 2011.","apa":"Xie, T., Müller, W., &#38; Letombe, F. (2011). HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. <i>Proceedings of Euromicro DSD 2011</i>. <a href=\"https://doi.org/10.1109/DSD.2011.83\">https://doi.org/10.1109/DSD.2011.83</a>"},"date_updated":"2025-02-26T14:44:15Z","publisher":"IEEE","author":[{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"Florian","last_name":"Letombe","full_name":"Letombe, Florian"}],"date_created":"2023-01-17T09:02:48Z","title":"HDL-Mutation Based Simulation Data Generation by Propagation Guided Search","doi":"10.1109/DSD.2011.83","publication":"Proceedings of Euromicro DSD 2011","type":"conference","abstract":[{"text":"HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.","lang":"eng"}],"status":"public","_id":"37002","department":[{"_id":"672"}],"user_id":"5786","keyword":["Hardware design languages","Cost function","Computational modeling","Fault detection","Data models","Analytical models","Testing"],"language":[{"iso":"eng"}]},{"citation":{"ama":"Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>","chicago":"Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based Verification of RTOS Properties.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">https://doi.org/10.1109/DATE.2010.5457130</a>.","ieee":"M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification of RTOS Properties,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>.","bibtex":"@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based Verification of RTOS Properties}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }","mla":"Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>.","short":"M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","apa":"Oliveira, M. F. S., Zabel, H., &#38; Müller, W. (2010). Assertion-Based Verification of RTOS Properties. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">https://doi.org/10.1109/DATE.2010.5457130</a>"},"year":"2010","place":"Dresden","conference":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"},"doi":"10.1109/DATE.2010.5457130","title":"Assertion-Based Verification of RTOS Properties","author":[{"last_name":"Oliveira","full_name":"Oliveira, Marcio F. S.","first_name":"Marcio F. S."},{"last_name":"Zabel","full_name":"Zabel, Henning","first_name":"Henning"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}],"date_created":"2023-01-17T09:15:10Z","date_updated":"2023-01-17T09:15:18Z","publisher":"IEEE","status":"public","abstract":[{"lang":"eng","text":"Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties."}],"publication":"Proceedings of DATE’10","type":"conference","language":[{"iso":"eng"}],"keyword":["Operating systems","Real time systems","Timing","Hardware","Analytical models","Embedded software","Software systems","Processor scheduling","Software performance","Performance analysis"],"department":[{"_id":"672"}],"user_id":"5786","_id":"37009"},{"publication":"Proceedings of DATE’10, Dresden","type":"conference","abstract":[{"lang":"eng","text":"Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study."}],"status":"public","_id":"37011","department":[{"_id":"672"}],"user_id":"5786","keyword":["Timing","Programming","Automotive engineering","Application software","Hardware","Computer architecture","Communication system software","Software architecture","Delay","Software standards"],"language":[{"iso":"eng"}],"place":"Dresden","year":"2010","citation":{"mla":"Klobedanz, Kay, et al. “Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study.” <i>Proceedings of DATE’10, Dresden</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457125\">10.1109/DATE.2010.5457125</a>.","bibtex":"@inproceedings{Klobedanz_Kuznik_Thuy_Müller_2010, place={Dresden}, title={Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5457125\">10.1109/DATE.2010.5457125</a>}, booktitle={Proceedings of DATE’10, Dresden}, publisher={IEEE}, author={Klobedanz, Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}, year={2010} }","short":"K. Klobedanz, C. Kuznik, A. Thuy, W. Müller, in: Proceedings of DATE’10, Dresden, IEEE, Dresden, 2010.","apa":"Klobedanz, K., Kuznik, C., Thuy, A., &#38; Müller, W. (2010). Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study. <i>Proceedings of DATE’10, Dresden</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5457125\">https://doi.org/10.1109/DATE.2010.5457125</a>","ama":"Klobedanz K, Kuznik C, Thuy A, Müller W. Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study. In: <i>Proceedings of DATE’10, Dresden</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457125\">10.1109/DATE.2010.5457125</a>","chicago":"Klobedanz, Kay, Christoph Kuznik, Andre Thuy, and Wolfgang Müller. “Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study.” In <i>Proceedings of DATE’10, Dresden</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5457125\">https://doi.org/10.1109/DATE.2010.5457125</a>.","ieee":"K. Klobedanz, C. Kuznik, A. Thuy, and W. Müller, “Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5457125\">10.1109/DATE.2010.5457125</a>."},"date_updated":"2023-01-17T09:19:46Z","publisher":"IEEE","date_created":"2023-01-17T09:19:36Z","author":[{"full_name":"Klobedanz, Kay","last_name":"Klobedanz","first_name":"Kay"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"full_name":"Thuy, Andre","last_name":"Thuy","first_name":"Andre"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}],"title":"Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study","doi":"10.1109/DATE.2010.5457125","conference":{"location":"Dresden","name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"}},{"abstract":[{"lang":"eng","text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms."}],"status":"public","publication":"Proceedings of DATE’10","type":"conference","keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"language":[{"iso":"eng"}],"_id":"37040","department":[{"_id":"672"}],"user_id":"5786","year":"2010","place":"Dresden","citation":{"apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }","mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>."},"publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","doi":"10.1109/DATE.2010.5456965","conference":{"location":"Dresden","name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"date_updated":"2023-01-17T10:47:37Z","publisher":"IEEE","author":[{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"last_name":"Di Guglielmo","full_name":"Di Guglielmo, Giuseppe","first_name":"Giuseppe"},{"full_name":"Fummi, Franco","last_name":"Fummi","first_name":"Franco"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"first_name":"Graziano","last_name":"Pravadelli","full_name":"Pravadelli, Graziano"},{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"}],"date_created":"2023-01-17T10:47:29Z"},{"status":"public","abstract":[{"text":"Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.","lang":"eng"}],"publication":"Proceedings of HLDVT2010","type":"conference","language":[{"iso":"eng"}],"keyword":["Hardware","Microprogramming","Application software","Timing","Protocols","Virtual prototyping","Real time systems","Sampling methods","Operating systems","Emulation"],"department":[{"_id":"672"}],"user_id":"5786","_id":"37053","citation":{"ieee":"W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.","chicago":"Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker. “Verification of Real-Time Properties for Hardware-Dependant Software.” In <i>Proceedings of HLDVT2010</i>. IEEE, 2010.","ama":"Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time Properties for Hardware-Dependant Software. In: <i>Proceedings of HLDVT2010</i>. IEEE; 2010.","apa":"Müller, W., da S. Oliveira, M. F., Zabel, H., &#38; Becker, M. (2010). Verification of Real-Time Properties for Hardware-Dependant Software. <i>Proceedings of HLDVT2010</i>. IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA.","mla":"Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant Software.” <i>Proceedings of HLDVT2010</i>, IEEE, 2010.","bibtex":"@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }","short":"W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of HLDVT2010, IEEE, 2010."},"year":"2010","publication_identifier":{"eisbn":["978-1-4244-7806-4"]},"conference":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT)","location":"Anaheim, FL, USA"},"title":"Verification of Real-Time Properties for Hardware-Dependant Software","author":[{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Marcio F.","last_name":"da S. Oliveira","full_name":"da S. Oliveira, Marcio F."},{"full_name":"Zabel, Henning","last_name":"Zabel","first_name":"Henning"},{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"}],"date_created":"2023-01-17T11:28:26Z","publisher":"IEEE","date_updated":"2023-01-17T11:28:30Z"},{"keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"language":[{"iso":"eng"}],"_id":"37039","user_id":"5786","abstract":[{"text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.","lang":"eng"}],"status":"public","publication":"Proceedings of DATE’10","type":"conference","title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","doi":"10.1109/DATE.2010.5456965","conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"},"publisher":"IEEE","date_updated":"2025-03-12T16:39:17Z","author":[{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"first_name":"Giuseppe","full_name":"Di Guglielmo, Giuseppe","last_name":"Di Guglielmo"},{"full_name":"Fummi, Franco","last_name":"Fummi","first_name":"Franco"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Graziano","last_name":"Pravadelli","full_name":"Pravadelli, Graziano"},{"first_name":"Tao","last_name":"Xie","full_name":"Xie, Tao"}],"date_created":"2023-01-17T10:44:46Z","place":"Dresden","year":"2010","citation":{"ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>.","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }","mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>"},"publication_identifier":{"eisbn":["978-3-9810801-6-2"]}},{"department":[{"_id":"672"}],"user_id":"5786","_id":"33814","language":[{"iso":"eng"}],"keyword":["Hardware-dependent Software","Systems Complexity","Productivity Gap"],"publication":"Hardware Dependent Software - Principles and Practice","type":"book_chapter","status":"public","editor":[{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"last_name":"Müller","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Rainer","full_name":"Dömer, Rainer","last_name":"Dömer"}],"abstract":[{"lang":"eng","text":"Rapidly rising system complexity has created a growing productivity gap in the\r\ndesign of electronic systems. One critical component is Hardware-dependent\r\nSoftware (HdS), the importance of which is often underestimated. In this chap-\r\nter, we introduce HdS and illustrate its role in the overall system design context.\r\nWe also provide a brief overview and define a basic HdS terminology and con-\r\nclude with a brief outlook over the following chapters in this book."}],"author":[{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"full_name":"Dömer, Rainer","last_name":"Dömer","first_name":"Rainer"}],"date_created":"2022-10-18T10:54:39Z","date_updated":"2022-10-18T10:54:56Z","publisher":"Springer Verlag","doi":"10.1007/978-1-4020-9436-1_1","title":"Hardware-dependent Software - Introduction and Overview","publication_identifier":{"isbn":["978-1-4020-9435-4"]},"page":"1-14","citation":{"apa":"Ecker, W., Müller, W., &#38; Dömer, R. (2009). Hardware-dependent Software - Introduction and Overview. In W. Ecker, W. Müller, &#38; R. Dömer (Eds.), <i>Hardware Dependent Software - Principles and Practice</i> (pp. 1–14). Springer Verlag. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">https://doi.org/10.1007/978-1-4020-9436-1_1</a>","mla":"Ecker, Wolfgang, et al. “Hardware-Dependent Software - Introduction and Overview.” <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang Ecker et al., Springer Verlag, 2009, pp. 1–14, doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">10.1007/978-1-4020-9436-1_1</a>.","bibtex":"@inbook{Ecker_Müller_Dömer_2009, place={Dordrecht}, title={Hardware-dependent Software - Introduction and Overview}, DOI={<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">10.1007/978-1-4020-9436-1_1</a>}, booktitle={Hardware Dependent Software - Principles and Practice}, publisher={Springer Verlag}, author={Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}, editor={Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}, year={2009}, pages={1–14} }","short":"W. Ecker, W. Müller, R. Dömer, in: W. Ecker, W. Müller, R. Dömer (Eds.), Hardware Dependent Software - Principles and Practice, Springer Verlag, Dordrecht, 2009, pp. 1–14.","chicago":"Ecker, Wolfgang, Wolfgang Müller, and Rainer Dömer. “Hardware-Dependent Software - Introduction and Overview.” In <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang Ecker, Wolfgang Müller, and Rainer Dömer, 1–14. Dordrecht: Springer Verlag, 2009. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">https://doi.org/10.1007/978-1-4020-9436-1_1</a>.","ieee":"W. Ecker, W. Müller, and R. Dömer, “Hardware-dependent Software - Introduction and Overview,” in <i>Hardware Dependent Software - Principles and Practice</i>, W. Ecker, W. Müller, and R. Dömer, Eds. Dordrecht: Springer Verlag, 2009, pp. 1–14.","ama":"Ecker W, Müller W, Dömer R. Hardware-dependent Software - Introduction and Overview. In: Ecker W, Müller W, Dömer R, eds. <i>Hardware Dependent Software - Principles and Practice</i>. Springer Verlag; 2009:1-14. doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">10.1007/978-1-4020-9436-1_1</a>"},"place":"Dordrecht","year":"2009"},{"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2262","language":[{"iso":"eng"}],"keyword":["EvoCache","evolvable hardware","computer architecture"],"type":"conference","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","status":"public","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"date_created":"2018-04-06T15:18:24Z","author":[{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:53:11Z","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","quality_controlled":"1","citation":{"ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>. IEEE Computer Society; 2009:11-18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 2009, pp. 11–18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, IEEE Computer Society, 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","apa":"Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18."},"page":"11-18","year":"2009","place":"Los Alamitos, CA, USA"},{"citation":{"chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, 447–54. IEEE, 2007. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>.","ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, Edinburgh, UK, 2007, pp. 447–454.","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>. IEEE; 2007:447-454. doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }","mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, IEEE, 2007, pp. 447–54, doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>.","short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.","apa":"Kaufmann, P., &#38; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i> (pp. 447–454). Edinburgh, UK: IEEE. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>"},"page":"447-454","year":"2007","publication_status":"published","publication_identifier":{"isbn":["076952866X","9780769528663"]},"conference":{"start_date":"2007-08-05","name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","location":"Edinburgh, UK","end_date":"2007-08-08"},"doi":"10.1109/ahs.2007.73","title":"MOVES: A Modular Framework for Hardware Evolution","date_created":"2019-01-08T09:52:43Z","author":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","date_updated":"2022-01-06T07:03:08Z","status":"public","abstract":[{"lang":"eng","text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits."}],"type":"conference","publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","language":[{"iso":"eng"}],"keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"user_id":"3118","department":[{"_id":"78"}],"_id":"6508"},{"title":"Server-based execution of periodic tasks on dynamically reconfigurable hardware","doi":"10.1049/iet-cdt:20060186","date_updated":"2022-01-06T06:50:49Z","volume":1,"author":[{"last_name":"Danne","full_name":"Danne, Klaus","first_name":"Klaus"},{"last_name":"Mühlenbernd","full_name":"Mühlenbernd, Roland","first_name":"Roland"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2019-07-10T11:10:54Z","year":"2007","intvolume":"         1","page":"295-302","citation":{"mla":"Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i>, vol. 1, no. 4, 2007, pp. 295–302, doi:<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>.","bibtex":"@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }","short":"K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.","apa":"Danne, K., Mühlenbernd, R., &#38; Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>, <i>1</i>(4), 295–302. <a href=\"https://doi.org/10.1049/iet-cdt:20060186\">https://doi.org/10.1049/iet-cdt:20060186</a>","ama":"Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>. 2007;1(4):295-302. doi:<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i> 1, no. 4 (2007): 295–302. <a href=\"https://doi.org/10.1049/iet-cdt:20060186\">https://doi.org/10.1049/iet-cdt:20060186</a>.","ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” <i>IET Computers Digital Techniques</i>, vol. 1, no. 4, pp. 295–302, 2007."},"publication_identifier":{"issn":["1751-8601"]},"issue":"4","keyword":["reconfigurable architectures","resource allocation","device reconfiguration time","dynamic hardware reconfiguration","dynamically reconfigurable hardware","light-weight runtime system","merge server distribute load","periodic real-time tasks","runtime system overheads","schedulability analysis","scheduling technique","server-based execution","synthesis tool flow"],"language":[{"iso":"eng"}],"_id":"10646","department":[{"_id":"78"}],"user_id":"3118","status":"public","publication":"IET Computers Digital Techniques","type":"journal_article"},{"publication_identifier":{"isbn":["978-0-7695-3071-0"]},"year":"2006","place":"Paphos, Cyprus","citation":{"apa":"Großmann, J., &#38; Müller, W. (2006). A Formal Behavioral Semantics for TestML. <i>Proc. of ISOLA 06</i>. <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">https://doi.org/10.1109/ISoLA.2006.37</a>","bibtex":"@inproceedings{Großmann_Müller_2006, place={Paphos, Cyprus}, title={A Formal Behavioral Semantics for TestML}, DOI={<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>}, booktitle={Proc. of ISOLA 06}, author={Großmann, Jürgen and Müller, Wolfgang}, year={2006} }","mla":"Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.” <i>Proc. of ISOLA 06</i>, 2006, doi:<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>.","short":"J. Großmann, W. Müller, in: Proc. of ISOLA 06, Paphos, Cyprus, 2006.","chicago":"Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.” In <i>Proc. of ISOLA 06</i>. Paphos, Cyprus, 2006. <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">https://doi.org/10.1109/ISoLA.2006.37</a>.","ieee":"J. Großmann and W. Müller, “A Formal Behavioral Semantics for TestML,” Paphos, Cyprus, 2006, doi: <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>.","ama":"Großmann J, Müller W. A Formal Behavioral Semantics for TestML. In: <i>Proc. of ISOLA 06</i>. ; 2006. doi:<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>"},"date_updated":"2023-01-23T12:06:26Z","date_created":"2023-01-23T12:00:06Z","author":[{"first_name":"Jürgen","full_name":"Großmann, Jürgen","last_name":"Großmann"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"title":"A Formal Behavioral Semantics for TestML","conference":{"location":"Paphos, Cyprus"},"doi":"10.1109/ISoLA.2006.37","publication":"Proc. of ISOLA 06","type":"conference","abstract":[{"lang":"eng","text":"TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML."}],"status":"public","_id":"38107","department":[{"_id":"672"}],"user_id":"5786","keyword":["System testing","Software testing","Automotive engineering","Automatic testing","Machinery production industries","Protocols","Hardware design languages","Samarium","XML","Computer industry"],"language":[{"iso":"eng"}]},{"_id":"39029","department":[{"_id":"672"}],"user_id":"5786","keyword":["Hardware","Unified modeling language","Virtual machining","Object oriented modeling","Field programmable gate arrays","Java","Microcontrollers","Embedded software","Real time systems","Documentation"],"language":[{"iso":"eng"}],"publication":"Proceedings of DATE’05","type":"conference","abstract":[{"text":"UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.","lang":"eng"}],"status":"public","publisher":"IEEE","date_updated":"2023-01-24T08:10:44Z","date_created":"2023-01-24T08:10:40Z","author":[{"first_name":"Tim","last_name":"Schattkowsky","full_name":"Schattkowsky, Tim"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"last_name":"Rettberg","full_name":"Rettberg, Achim","first_name":"Achim"}],"title":"A Model-Based Approach for Executable Specification on Reconfigurable Hardware","doi":"10.1109/DATE.2005.20","publication_identifier":{"isbn":["0-7695-2288-2"]},"place":"Munich, Germany ","year":"2005","citation":{"apa":"Schattkowsky, T., Müller, W., &#38; Rettberg, A. (2005). A Model-Based Approach for Executable Specification on Reconfigurable Hardware. <i>Proceedings of DATE’05</i>. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>","mla":"Schattkowsky, Tim, et al. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” <i>Proceedings of DATE’05</i>, IEEE, 2005, doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>.","short":"T. Schattkowsky, W. Müller, A. Rettberg, in: Proceedings of DATE’05, IEEE, Munich, Germany , 2005.","bibtex":"@inproceedings{Schattkowsky_Müller_Rettberg_2005, place={Munich, Germany }, title={A Model-Based Approach for Executable Specification on Reconfigurable Hardware}, DOI={<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>}, booktitle={Proceedings of DATE’05}, publisher={IEEE}, author={Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}, year={2005} }","ama":"Schattkowsky T, Müller W, Rettberg A. A Model-Based Approach for Executable Specification on Reconfigurable Hardware. In: <i>Proceedings of DATE’05</i>. IEEE; 2005. doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>","chicago":"Schattkowsky, Tim, Wolfgang Müller, and Achim Rettberg. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” In <i>Proceedings of DATE’05</i>. Munich, Germany : IEEE, 2005. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>.","ieee":"T. Schattkowsky, W. Müller, and A. Rettberg, “A Model-Based Approach for Executable Specification on Reconfigurable Hardware,” 2005, doi: <a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>."}},{"year":"2005","place":"Las Vegas, NV","citation":{"ama":"Schattkowsky T, Müller W. A UML Virtual Machine for Embedded Systems. In: <i>Proceedings of ISNG 05</i>. ; 2005.","ieee":"T. Schattkowsky and W. Müller, “A UML Virtual Machine for Embedded Systems,” 2005.","chicago":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” In <i>Proceedings of ISNG 05</i>. Las Vegas, NV, 2005.","short":"T. Schattkowsky, W. Müller, in: Proceedings of ISNG 05, Las Vegas, NV, 2005.","mla":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” <i>Proceedings of ISNG 05</i>, 2005.","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Las Vegas, NV}, title={A UML Virtual Machine for Embedded Systems}, booktitle={Proceedings of ISNG 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }","apa":"Schattkowsky, T., &#38; Müller, W. (2005). A UML Virtual Machine for Embedded Systems. <i>Proceedings of ISNG 05</i>."},"title":"A UML Virtual Machine for Embedded Systems","date_updated":"2023-01-24T08:12:26Z","date_created":"2023-01-24T08:12:20Z","author":[{"last_name":"Schattkowsky","full_name":"Schattkowsky, Tim","first_name":"Tim"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"abstract":[{"lang":"eng","text":"StateCharts are well accepted for embedded systems\r\nspecification for various applications. However, for the\r\nspecification of complex systems they have several\r\nlimitations. In this article, we present a novel approach to\r\nefficiently execute an UML 2.0 subset for embedded real-\r\ntime systems implementation with focus on hardware\r\ninterrupts, software exceptions, and timeouts. We\r\nintroduce a UML Virtual Machine, which directly\r\nexecutes sequence diagrams, which are embedded into\r\nhierarchically structured state transition diagrams.\r\nWhereas state diagrams are directly executed as\r\nEmbedded State Machines (ESMs), sequence diagrams\r\nare translated into UVM Bytecode. The final UVM\r\nexecution is performed by the interaction of the ESM and\r\nthe Bytecode Interpreter. Due to our completely model-\r\nbased approach, the UVM runtime kernel is easily\r\nadaptable and scalable to different scheduling and\r\nmemory management strategies."}],"status":"public","type":"conference","publication":"Proceedings of ISNG 05","keyword":["UML","Executable Models","Hardware/Software Co-design","Virtual Machine","Embedded Systems"],"language":[{"iso":"eng"}],"_id":"39030","user_id":"5786","department":[{"_id":"672"}]},{"date_updated":"2023-01-24T08:18:27Z","author":[{"full_name":"Schattkowsky, Tim","last_name":"Schattkowsky","first_name":"Tim"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"date_created":"2023-01-24T08:18:10Z","title":"Transformation of UML State Machines for Direct Execution","doi":"10.1109/VLHCC.2005.64","publication_identifier":{"isbn":["0-7695-2443-5"]},"year":"2005","place":"Dallas, TX, USA","citation":{"apa":"Schattkowsky, T., &#38; Müller, W. (2005). Transformation of UML State Machines for Direct Execution. <i>Proceedings of VL/HCC 05</i>. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Dallas, TX, USA}, title={Transformation of UML State Machines for Direct Execution}, DOI={<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>}, booktitle={Proceedings of VL/HCC 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }","mla":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” <i>Proceedings of VL/HCC 05</i>, 2005, doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","short":"T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA, 2005.","chicago":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” In <i>Proceedings of VL/HCC 05</i>. Dallas, TX, USA, 2005. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>.","ieee":"T. Schattkowsky and W. Müller, “Transformation of UML State Machines for Direct Execution,” 2005, doi: <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","ama":"Schattkowsky T, Müller W. Transformation of UML State Machines for Direct Execution. In: <i>Proceedings of VL/HCC 05</i>. ; 2005. doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>"},"_id":"39032","user_id":"5786","department":[{"_id":"672"}],"keyword":["Unified modeling language","Software design","Virtual machining","Embedded system","Programming","Documentation","Hardware","Computer languages","Operating systems","Runtime"],"language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of VL/HCC 05","abstract":[{"text":"Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.","lang":"eng"}],"status":"public"},{"status":"public","abstract":[{"lang":"eng","text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. "}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","type":"conference","keyword":["hardware virtualization"],"department":[{"_id":"518"},{"_id":"78"}],"user_id":"24135","_id":"2415","page":"63-69","citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2004, pp. 63–69.","bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }","apa":"Plessl, C., &#38; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 63–69). CSREA Press.","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2004:63-69.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2004, pp. 63–69.","chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 63–69. CSREA Press, 2004."},"year":"2004","title":"Virtualization of Hardware – Introduction and Survey","date_created":"2018-04-17T14:45:57Z","author":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"publisher":"CSREA Press","date_updated":"2022-01-06T06:56:08Z"},{"language":[{"iso":"eng"}],"keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"publication":"IEEE Micro","date_created":"2023-01-25T09:33:18Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","title":"VLSI technologies for artificial neural networks","issue":"6","year":"2002","department":[{"_id":"59"}],"user_id":"20179","_id":"39925","type":"journal_article","status":"public","volume":9,"author":[{"full_name":"Goser, K.","last_name":"Goser","first_name":"K."},{"id":"20179","full_name":"Hilleringmann, Ulrich","last_name":"Hilleringmann","first_name":"Ulrich"},{"first_name":"U.","full_name":"Rueckert, U.","last_name":"Rueckert"},{"first_name":"K.","full_name":"Schumacher, K.","last_name":"Schumacher"}],"date_updated":"2023-03-21T09:57:17Z","doi":"10.1109/40.42985","publication_identifier":{"issn":["0272-1732"]},"publication_status":"published","intvolume":"         9","page":"28-44","citation":{"ieee":"K. Goser, U. Hilleringmann, U. Rueckert, and K. Schumacher, “VLSI technologies for artificial neural networks,” <i>IEEE Micro</i>, vol. 9, no. 6, pp. 28–44, 2002, doi: <a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>.","chicago":"Goser, K., Ulrich Hilleringmann, U. Rueckert, and K. Schumacher. “VLSI Technologies for Artificial Neural Networks.” <i>IEEE Micro</i> 9, no. 6 (2002): 28–44. <a href=\"https://doi.org/10.1109/40.42985\">https://doi.org/10.1109/40.42985</a>.","ama":"Goser K, Hilleringmann U, Rueckert U, Schumacher K. VLSI technologies for artificial neural networks. <i>IEEE Micro</i>. 2002;9(6):28-44. doi:<a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>","short":"K. Goser, U. Hilleringmann, U. Rueckert, K. Schumacher, IEEE Micro 9 (2002) 28–44.","mla":"Goser, K., et al. “VLSI Technologies for Artificial Neural Networks.” <i>IEEE Micro</i>, vol. 9, no. 6, Institute of Electrical and Electronics Engineers (IEEE), 2002, pp. 28–44, doi:<a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>.","bibtex":"@article{Goser_Hilleringmann_Rueckert_Schumacher_2002, title={VLSI technologies for artificial neural networks}, volume={9}, DOI={<a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>}, number={6}, journal={IEEE Micro}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Goser, K. and Hilleringmann, Ulrich and Rueckert, U. and Schumacher, K.}, year={2002}, pages={28–44} }","apa":"Goser, K., Hilleringmann, U., Rueckert, U., &#38; Schumacher, K. (2002). VLSI technologies for artificial neural networks. <i>IEEE Micro</i>, <i>9</i>(6), 28–44. <a href=\"https://doi.org/10.1109/40.42985\">https://doi.org/10.1109/40.42985</a>"}},{"date_updated":"2023-03-22T10:36:45Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","volume":9,"date_created":"2023-01-25T09:33:50Z","author":[{"full_name":"Goser, K.","last_name":"Goser","first_name":"K."},{"last_name":"Hilleringmann","id":"20179","full_name":"Hilleringmann, Ulrich","first_name":"Ulrich"},{"last_name":"Rueckert","full_name":"Rueckert, U.","first_name":"U."},{"last_name":"Schumacher","full_name":"Schumacher, K.","first_name":"K."}],"title":"VLSI technologies for artificial neural networks","doi":"10.1109/40.42985","publication_identifier":{"issn":["0272-1732"]},"publication_status":"published","issue":"6","year":"2002","intvolume":"         9","page":"28-44","citation":{"ama":"Goser K, Hilleringmann U, Rueckert U, Schumacher K. VLSI technologies for artificial neural networks. <i>IEEE Micro</i>. 2002;9(6):28-44. doi:<a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>","ieee":"K. Goser, U. Hilleringmann, U. Rueckert, and K. Schumacher, “VLSI technologies for artificial neural networks,” <i>IEEE Micro</i>, vol. 9, no. 6, pp. 28–44, 2002, doi: <a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>.","chicago":"Goser, K., Ulrich Hilleringmann, U. Rueckert, and K. Schumacher. “VLSI Technologies for Artificial Neural Networks.” <i>IEEE Micro</i> 9, no. 6 (2002): 28–44. <a href=\"https://doi.org/10.1109/40.42985\">https://doi.org/10.1109/40.42985</a>.","short":"K. Goser, U. Hilleringmann, U. Rueckert, K. Schumacher, IEEE Micro 9 (2002) 28–44.","mla":"Goser, K., et al. “VLSI Technologies for Artificial Neural Networks.” <i>IEEE Micro</i>, vol. 9, no. 6, Institute of Electrical and Electronics Engineers (IEEE), 2002, pp. 28–44, doi:<a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>.","bibtex":"@article{Goser_Hilleringmann_Rueckert_Schumacher_2002, title={VLSI technologies for artificial neural networks}, volume={9}, DOI={<a href=\"https://doi.org/10.1109/40.42985\">10.1109/40.42985</a>}, number={6}, journal={IEEE Micro}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Goser, K. and Hilleringmann, Ulrich and Rueckert, U. and Schumacher, K.}, year={2002}, pages={28–44} }","apa":"Goser, K., Hilleringmann, U., Rueckert, U., &#38; Schumacher, K. (2002). VLSI technologies for artificial neural networks. <i>IEEE Micro</i>, <i>9</i>(6), 28–44. <a href=\"https://doi.org/10.1109/40.42985\">https://doi.org/10.1109/40.42985</a>"},"_id":"39926","department":[{"_id":"59"}],"user_id":"20179","keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"language":[{"iso":"eng"}],"publication":"IEEE Micro","type":"journal_article","status":"public"}]