---
_id: '53213'
article_number: '101027'
author:
- first_name: Arman
full_name: Amiri, Arman
last_name: Amiri
- first_name: Madjid
full_name: Tavana, Madjid
id: '31858'
last_name: Tavana
- first_name: Hosein
full_name: Arman, Hosein
last_name: Arman
citation:
ama: Amiri A, Tavana M, Arman H. An Integrated Fuzzy Analytic Network Process and
Fuzzy Regression Method for Bitcoin Price Prediction. Internet of Things.
2024;25. doi:10.1016/j.iot.2023.101027
apa: Amiri, A., Tavana, M., & Arman, H. (2024). An Integrated Fuzzy Analytic
Network Process and Fuzzy Regression Method for Bitcoin Price Prediction. Internet
of Things, 25, Article 101027. https://doi.org/10.1016/j.iot.2023.101027
bibtex: '@article{Amiri_Tavana_Arman_2024, title={An Integrated Fuzzy Analytic Network
Process and Fuzzy Regression Method for Bitcoin Price Prediction}, volume={25},
DOI={10.1016/j.iot.2023.101027},
number={101027}, journal={Internet of Things}, publisher={Elsevier BV}, author={Amiri,
Arman and Tavana, Madjid and Arman, Hosein}, year={2024} }'
chicago: Amiri, Arman, Madjid Tavana, and Hosein Arman. “An Integrated Fuzzy Analytic
Network Process and Fuzzy Regression Method for Bitcoin Price Prediction.” Internet
of Things 25 (2024). https://doi.org/10.1016/j.iot.2023.101027.
ieee: 'A. Amiri, M. Tavana, and H. Arman, “An Integrated Fuzzy Analytic Network
Process and Fuzzy Regression Method for Bitcoin Price Prediction,” Internet
of Things, vol. 25, Art. no. 101027, 2024, doi: 10.1016/j.iot.2023.101027.'
mla: Amiri, Arman, et al. “An Integrated Fuzzy Analytic Network Process and Fuzzy
Regression Method for Bitcoin Price Prediction.” Internet of Things, vol.
25, 101027, Elsevier BV, 2024, doi:10.1016/j.iot.2023.101027.
short: A. Amiri, M. Tavana, H. Arman, Internet of Things 25 (2024).
date_created: 2024-04-04T13:34:26Z
date_updated: 2024-04-15T13:08:17Z
department:
- _id: '277'
doi: 10.1016/j.iot.2023.101027
intvolume: ' 25'
keyword:
- Management of Technology and Innovation
- Artificial Intelligence
- Computer Science Applications
- Hardware and Architecture
- Engineering (miscellaneous)
- Information Systems
- Computer Science (miscellaneous)
- Software
language:
- iso: eng
publication: Internet of Things
publication_identifier:
issn:
- 2542-6605
publication_status: published
publisher: Elsevier BV
status: public
title: An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for
Bitcoin Price Prediction
type: journal_article
user_id: '51811'
volume: 25
year: '2024'
...
---
_id: '53212'
author:
- first_name: Ehsan
full_name: Mahmoodi, Ehsan
last_name: Mahmoodi
- first_name: Masood
full_name: Fathi, Masood
last_name: Fathi
- first_name: Madjid
full_name: Tavana, Madjid
id: '31858'
last_name: Tavana
- first_name: Morteza
full_name: Ghobakhloo, Morteza
last_name: Ghobakhloo
- first_name: Amos H.C.
full_name: Ng, Amos H.C.
last_name: Ng
citation:
ama: Mahmoodi E, Fathi M, Tavana M, Ghobakhloo M, Ng AHC. Data-driven simulation-based
decision support system for resource allocation in industry 4.0 and smart manufacturing.
Journal of Manufacturing Systems. 2024;72:287-307. doi:10.1016/j.jmsy.2023.11.019
apa: Mahmoodi, E., Fathi, M., Tavana, M., Ghobakhloo, M., & Ng, A. H. C. (2024).
Data-driven simulation-based decision support system for resource allocation in
industry 4.0 and smart manufacturing. Journal of Manufacturing Systems,
72, 287–307. https://doi.org/10.1016/j.jmsy.2023.11.019
bibtex: '@article{Mahmoodi_Fathi_Tavana_Ghobakhloo_Ng_2024, title={Data-driven simulation-based
decision support system for resource allocation in industry 4.0 and smart manufacturing},
volume={72}, DOI={10.1016/j.jmsy.2023.11.019},
journal={Journal of Manufacturing Systems}, publisher={Elsevier BV}, author={Mahmoodi,
Ehsan and Fathi, Masood and Tavana, Madjid and Ghobakhloo, Morteza and Ng, Amos
H.C.}, year={2024}, pages={287–307} }'
chicago: 'Mahmoodi, Ehsan, Masood Fathi, Madjid Tavana, Morteza Ghobakhloo, and
Amos H.C. Ng. “Data-Driven Simulation-Based Decision Support System for Resource
Allocation in Industry 4.0 and Smart Manufacturing.” Journal of Manufacturing
Systems 72 (2024): 287–307. https://doi.org/10.1016/j.jmsy.2023.11.019.'
ieee: 'E. Mahmoodi, M. Fathi, M. Tavana, M. Ghobakhloo, and A. H. C. Ng, “Data-driven
simulation-based decision support system for resource allocation in industry 4.0
and smart manufacturing,” Journal of Manufacturing Systems, vol. 72, pp.
287–307, 2024, doi: 10.1016/j.jmsy.2023.11.019.'
mla: Mahmoodi, Ehsan, et al. “Data-Driven Simulation-Based Decision Support System
for Resource Allocation in Industry 4.0 and Smart Manufacturing.” Journal of
Manufacturing Systems, vol. 72, Elsevier BV, 2024, pp. 287–307, doi:10.1016/j.jmsy.2023.11.019.
short: E. Mahmoodi, M. Fathi, M. Tavana, M. Ghobakhloo, A.H.C. Ng, Journal of Manufacturing
Systems 72 (2024) 287–307.
date_created: 2024-04-04T13:33:48Z
date_updated: 2024-04-15T13:08:02Z
department:
- _id: '277'
doi: 10.1016/j.jmsy.2023.11.019
intvolume: ' 72'
keyword:
- Industrial and Manufacturing Engineering
- Hardware and Architecture
- Software
- Control and Systems Engineering
language:
- iso: eng
page: 287-307
publication: Journal of Manufacturing Systems
publication_identifier:
issn:
- 0278-6125
publication_status: published
publisher: Elsevier BV
status: public
title: Data-driven simulation-based decision support system for resource allocation
in industry 4.0 and smart manufacturing
type: journal_article
user_id: '51811'
volume: 72
year: '2024'
...
---
_id: '46264'
abstract:
- lang: eng
text: "System-level interconnects provide the\r\nbackbone for increasingly complex
systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can
lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis
article presents an approach for periodic in-system testing\r\nwhich maintains
a reliability profile to detect potential\r\nproblems before they actually cause
a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement
and test, it minimizes the stress induced by the\r\ntest itself and contributes
to the self-healing of system-induced\r\nelectromigration degradations. "
article_type: original
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect
BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849
apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Workload-Aware
Periodic Interconnect BIST. IEEE Design &Test, 1–1. https://doi.org/10.1109/mdat.2023.3298849
bibtex: '@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware
Periodic Interconnect BIST}, DOI={10.1109/mdat.2023.3298849},
journal={IEEE Design &Test}, publisher={Institute of Electrical and Electronics
Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and
Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }'
chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich.
“Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, 2023,
1–1. https://doi.org/10.1109/mdat.2023.3298849.
ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic
Interconnect BIST,” IEEE Design &Test, pp. 1–1, 2023, doi: 10.1109/mdat.2023.3298849.'
mla: Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.”
IEEE Design &Test, Institute of Electrical and Electronics Engineers
(IEEE), 2023, pp. 1–1, doi:10.1109/mdat.2023.3298849.
short: S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test
(2023) 1–1.
date_created: 2023-08-02T11:07:43Z
date_updated: 2024-03-22T17:15:10Z
department:
- _id: '48'
doi: 10.1109/mdat.2023.3298849
keyword:
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315
page: 1-1
publication: IEEE Design &Test
publication_identifier:
issn:
- 2168-2356
- 2168-2364
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Workload-Aware Periodic Interconnect BIST
type: journal_article
user_id: '209'
year: '2023'
...
---
_id: '53220'
article_number: '100786'
author:
- first_name: Madjid
full_name: Tavana, Madjid
id: '31858'
last_name: Tavana
- first_name: Arash
full_name: Khalili Nasr, Arash
last_name: Khalili Nasr
- first_name: Alireza Barati
full_name: Ahmadabadi, Alireza Barati
last_name: Ahmadabadi
- first_name: Alireza Shamekhi
full_name: Amiri, Alireza Shamekhi
last_name: Amiri
- first_name: Hassan
full_name: Mina, Hassan
last_name: Mina
citation:
ama: Tavana M, Khalili Nasr A, Ahmadabadi AB, Amiri AS, Mina H. An interval multi-criteria
decision-making model for evaluating blockchain-IoT technology in supply chain
networks. Internet of Things. 2023;22. doi:10.1016/j.iot.2023.100786
apa: Tavana, M., Khalili Nasr, A., Ahmadabadi, A. B., Amiri, A. S., & Mina,
H. (2023). An interval multi-criteria decision-making model for evaluating blockchain-IoT
technology in supply chain networks. Internet of Things, 22, Article
100786. https://doi.org/10.1016/j.iot.2023.100786
bibtex: '@article{Tavana_Khalili Nasr_Ahmadabadi_Amiri_Mina_2023, title={An interval
multi-criteria decision-making model for evaluating blockchain-IoT technology
in supply chain networks}, volume={22}, DOI={10.1016/j.iot.2023.100786},
number={100786}, journal={Internet of Things}, publisher={Elsevier BV}, author={Tavana,
Madjid and Khalili Nasr, Arash and Ahmadabadi, Alireza Barati and Amiri, Alireza
Shamekhi and Mina, Hassan}, year={2023} }'
chicago: Tavana, Madjid, Arash Khalili Nasr, Alireza Barati Ahmadabadi, Alireza
Shamekhi Amiri, and Hassan Mina. “An Interval Multi-Criteria Decision-Making Model
for Evaluating Blockchain-IoT Technology in Supply Chain Networks.” Internet
of Things 22 (2023). https://doi.org/10.1016/j.iot.2023.100786.
ieee: 'M. Tavana, A. Khalili Nasr, A. B. Ahmadabadi, A. S. Amiri, and H. Mina, “An
interval multi-criteria decision-making model for evaluating blockchain-IoT technology
in supply chain networks,” Internet of Things, vol. 22, Art. no. 100786,
2023, doi: 10.1016/j.iot.2023.100786.'
mla: Tavana, Madjid, et al. “An Interval Multi-Criteria Decision-Making Model for
Evaluating Blockchain-IoT Technology in Supply Chain Networks.” Internet of
Things, vol. 22, 100786, Elsevier BV, 2023, doi:10.1016/j.iot.2023.100786.
short: M. Tavana, A. Khalili Nasr, A.B. Ahmadabadi, A.S. Amiri, H. Mina, Internet
of Things 22 (2023).
date_created: 2024-04-04T13:49:53Z
date_updated: 2024-04-15T13:10:41Z
department:
- _id: '277'
doi: 10.1016/j.iot.2023.100786
intvolume: ' 22'
keyword:
- Management of Technology and Innovation
- Artificial Intelligence
- Computer Science Applications
- Hardware and Architecture
- Engineering (miscellaneous)
- Information Systems
- Computer Science (miscellaneous)
- Software
language:
- iso: eng
publication: Internet of Things
publication_identifier:
issn:
- 2542-6605
publication_status: published
publisher: Elsevier BV
status: public
title: An interval multi-criteria decision-making model for evaluating blockchain-IoT
technology in supply chain networks
type: journal_article
user_id: '51811'
volume: 22
year: '2023'
...
---
_id: '45361'
abstract:
- lang: eng
text: The non-orthogonal local submatrix method applied to electronic structure–based
molecular dynamics simulations is shown to exceed 1.1 EFLOP/s in FP16/FP32-mixed
floating-point arithmetic when using 4400 NVIDIA A100 GPUs of the Perlmutter system.
This is enabled by a modification of the original method that pushes the sustained
fraction of the peak performance to about 80%. Example calculations are performed
for SARS-CoV-2 spike proteins with up to 83 million atoms.
article_number: '109434202311776'
article_type: original
author:
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-539
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Hossam
full_name: Elgabarty, Hossam
id: '60250'
last_name: Elgabarty
orcid: 0000-0002-4945-1481
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Schade R, Kenter T, Elgabarty H, Lass M, Kühne T, Plessl C. Breaking the exascale
barrier for the electronic structure problem in ab-initio molecular dynamics.
The International Journal of High Performance Computing Applications. Published
online 2023. doi:10.1177/10943420231177631
apa: Schade, R., Kenter, T., Elgabarty, H., Lass, M., Kühne, T., & Plessl, C.
(2023). Breaking the exascale barrier for the electronic structure problem in
ab-initio molecular dynamics. The International Journal of High Performance
Computing Applications, Article 109434202311776. https://doi.org/10.1177/10943420231177631
bibtex: '@article{Schade_Kenter_Elgabarty_Lass_Kühne_Plessl_2023, title={Breaking
the exascale barrier for the electronic structure problem in ab-initio molecular
dynamics}, DOI={10.1177/10943420231177631},
number={109434202311776}, journal={The International Journal of High Performance
Computing Applications}, publisher={SAGE Publications}, author={Schade, Robert
and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Kühne, Thomas and
Plessl, Christian}, year={2023} }'
chicago: Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Thomas Kühne,
and Christian Plessl. “Breaking the Exascale Barrier for the Electronic Structure
Problem in Ab-Initio Molecular Dynamics.” The International Journal of High
Performance Computing Applications, 2023. https://doi.org/10.1177/10943420231177631.
ieee: 'R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, and C. Plessl, “Breaking
the exascale barrier for the electronic structure problem in ab-initio molecular
dynamics,” The International Journal of High Performance Computing Applications,
Art. no. 109434202311776, 2023, doi: 10.1177/10943420231177631.'
mla: Schade, Robert, et al. “Breaking the Exascale Barrier for the Electronic Structure
Problem in Ab-Initio Molecular Dynamics.” The International Journal of High
Performance Computing Applications, 109434202311776, SAGE Publications, 2023,
doi:10.1177/10943420231177631.
short: R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, C. Plessl, The International
Journal of High Performance Computing Applications (2023).
date_created: 2023-05-30T09:19:09Z
date_updated: 2023-08-02T15:04:53Z
department:
- _id: '27'
- _id: '518'
doi: 10.1177/10943420231177631
keyword:
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://journals.sagepub.com/doi/10.1177/10943420231177631
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: The International Journal of High Performance Computing Applications
publication_identifier:
issn:
- 1094-3420
- 1741-2846
publication_status: published
publisher: SAGE Publications
quality_controlled: '1'
status: public
title: Breaking the exascale barrier for the electronic structure problem in ab-initio
molecular dynamics
type: journal_article
user_id: '75963'
year: '2023'
...
---
_id: '29769'
abstract:
- lang: eng
text: 'Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender
Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe
zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden
zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in
eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können
auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei
zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen
oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt
sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren
Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung
von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers
mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen
den Trojaner ``Heimtückische LUT'''' stellen wir die allererste erfolgreiche Gegenmaßnahme
vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene
direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren
ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen
für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher
bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom
in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff
zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer
vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.'
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable
systems, the defenders perspective which corresponds to the bitstream-level Trojan
detection technique, and the attackers perspective which corresponds to a novel
FPGA Trojan attack. From the defender's perspective, we introduce a first-ever
successful pre-configuration countermeasure against the ``Malicious LUT''-hardware
Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present
the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers
perspective, we present a novel attack that leverages malicious routing of the
inserted Trojan circuit to acquire a dormant state even in the generated and transmitted
bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected
in the bitstream, the presented attack can currently neither be prevented by conventional
testing and verification methods nor by bitstream-level verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University,
Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
apa: Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271
bibtex: '@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable
Computing}, DOI={10.17619/UNIPB/1-1271},
publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab},
year={2022} }'
chicago: 'Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing.
Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.'
ieee: 'Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn
University, Paderborn, Germany, 2022.'
mla: Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.
short: Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University,
Paderborn, Germany, Paderborn, 2022.
date_created: 2022-02-07T14:02:36Z
date_updated: 2022-11-30T13:39:01Z
ddc:
- '004'
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1271
has_accepted_license: '1'
keyword:
- FPGA Security
- Hardware Trojans
- Bitstream-level Trojans
- Bitstream Verification
language:
- iso: eng
main_file_link:
- open_access: '1'
url: "\turn:nbn:de:hbz:466:2-40303"
oa: '1'
place: Paderborn
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication_status: published
publisher: ' Paderborn University, Paderborn, Germany'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Trojans in Reconfigurable Computing
type: dissertation
user_id: '477'
year: '2022'
...
---
_id: '45847'
abstract:
- lang: eng
text: "Abstract\r\n In this paper,
we investigate the parameterized complexity of model checking for Dependence and
Independence logic, which are well studied logics in the area of Team Semantics.
We start with a list of nine immediate parameterizations for this problem, namely
the number of disjunctions (i.e. splits)/(free) variables/universal quantifiers,
formula-size, the tree-width of the Gaifman graph of the input structure, the
size of the universe/team and the arity of dependence atoms. We present a comprehensive
picture of the parameterized complexity of model checking and obtain a division
of the problem into tractable and various intractable degrees. Furthermore, we
also consider the complexity of the most important variants (data and expression
complexity) of the model checking problem by fixing parts of the input."
author:
- first_name: Juha
full_name: Kontinen, Juha
last_name: Kontinen
- first_name: Arne
full_name: Meier, Arne
last_name: Meier
- first_name: Yasir
full_name: Mahmood, Yasir
id: '99353'
last_name: Mahmood
citation:
ama: Kontinen J, Meier A, Mahmood Y. A parameterized view on the complexity of dependence
and independence logic. Journal of Logic and Computation. 2022;32(8):1624-1644.
doi:10.1093/logcom/exac070
apa: Kontinen, J., Meier, A., & Mahmood, Y. (2022). A parameterized view on
the complexity of dependence and independence logic. Journal of Logic and Computation,
32(8), 1624–1644. https://doi.org/10.1093/logcom/exac070
bibtex: '@article{Kontinen_Meier_Mahmood_2022, title={A parameterized view on the
complexity of dependence and independence logic}, volume={32}, DOI={10.1093/logcom/exac070},
number={8}, journal={Journal of Logic and Computation}, publisher={Oxford University
Press (OUP)}, author={Kontinen, Juha and Meier, Arne and Mahmood, Yasir}, year={2022},
pages={1624–1644} }'
chicago: 'Kontinen, Juha, Arne Meier, and Yasir Mahmood. “A Parameterized View on
the Complexity of Dependence and Independence Logic.” Journal of Logic and
Computation 32, no. 8 (2022): 1624–44. https://doi.org/10.1093/logcom/exac070.'
ieee: 'J. Kontinen, A. Meier, and Y. Mahmood, “A parameterized view on the complexity
of dependence and independence logic,” Journal of Logic and Computation,
vol. 32, no. 8, pp. 1624–1644, 2022, doi: 10.1093/logcom/exac070.'
mla: Kontinen, Juha, et al. “A Parameterized View on the Complexity of Dependence
and Independence Logic.” Journal of Logic and Computation, vol. 32, no.
8, Oxford University Press (OUP), 2022, pp. 1624–44, doi:10.1093/logcom/exac070.
short: J. Kontinen, A. Meier, Y. Mahmood, Journal of Logic and Computation 32 (2022)
1624–1644.
date_created: 2023-07-03T11:36:55Z
date_updated: 2024-06-04T16:06:37Z
doi: 10.1093/logcom/exac070
extern: '1'
intvolume: ' 32'
issue: '8'
keyword:
- Logic
- Hardware and Architecture
- Arts and Humanities (miscellaneous)
- Software
- Theoretical Computer Science
language:
- iso: eng
page: 1624-1644
publication: Journal of Logic and Computation
publication_identifier:
issn:
- 0955-792X
- 1465-363X
publication_status: published
publisher: Oxford University Press (OUP)
status: public
title: A parameterized view on the complexity of dependence and independence logic
type: journal_article
user_id: '99353'
volume: 32
year: '2022'
...
---
_id: '33684'
article_number: '102920'
author:
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-539
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Hossam
full_name: Elgabarty, Hossam
id: '60250'
last_name: Elgabarty
orcid: 0000-0002-4945-1481
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Ole
full_name: Schütt, Ole
last_name: Schütt
- first_name: Alfio
full_name: Lazzaro, Alfio
last_name: Lazzaro
- first_name: Hans
full_name: Pabst, Hans
last_name: Pabst
- first_name: Stephan
full_name: Mohr, Stephan
last_name: Mohr
- first_name: Jürg
full_name: Hutter, Jürg
last_name: Hutter
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Schade R, Kenter T, Elgabarty H, et al. Towards electronic structure-based
ab-initio molecular dynamics simulations with hundreds of millions of atoms. Parallel
Computing. 2022;111. doi:10.1016/j.parco.2022.102920
apa: Schade, R., Kenter, T., Elgabarty, H., Lass, M., Schütt, O., Lazzaro, A., Pabst,
H., Mohr, S., Hutter, J., Kühne, T., & Plessl, C. (2022). Towards electronic
structure-based ab-initio molecular dynamics simulations with hundreds of millions
of atoms. Parallel Computing, 111, Article 102920. https://doi.org/10.1016/j.parco.2022.102920
bibtex: '@article{Schade_Kenter_Elgabarty_Lass_Schütt_Lazzaro_Pabst_Mohr_Hutter_Kühne_et
al._2022, title={Towards electronic structure-based ab-initio molecular dynamics
simulations with hundreds of millions of atoms}, volume={111}, DOI={10.1016/j.parco.2022.102920},
number={102920}, journal={Parallel Computing}, publisher={Elsevier BV}, author={Schade,
Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Schütt,
Ole and Lazzaro, Alfio and Pabst, Hans and Mohr, Stephan and Hutter, Jürg and
Kühne, Thomas and et al.}, year={2022} }'
chicago: Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Ole Schütt,
Alfio Lazzaro, Hans Pabst, et al. “Towards Electronic Structure-Based Ab-Initio
Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” Parallel
Computing 111 (2022). https://doi.org/10.1016/j.parco.2022.102920.
ieee: 'R. Schade et al., “Towards electronic structure-based ab-initio molecular
dynamics simulations with hundreds of millions of atoms,” Parallel Computing,
vol. 111, Art. no. 102920, 2022, doi: 10.1016/j.parco.2022.102920.'
mla: Schade, Robert, et al. “Towards Electronic Structure-Based Ab-Initio Molecular
Dynamics Simulations with Hundreds of Millions of Atoms.” Parallel Computing,
vol. 111, 102920, Elsevier BV, 2022, doi:10.1016/j.parco.2022.102920.
short: R. Schade, T. Kenter, H. Elgabarty, M. Lass, O. Schütt, A. Lazzaro, H. Pabst,
S. Mohr, J. Hutter, T. Kühne, C. Plessl, Parallel Computing 111 (2022).
date_created: 2022-10-11T08:17:02Z
date_updated: 2023-08-02T15:03:55Z
department:
- _id: '613'
- _id: '27'
- _id: '518'
doi: 10.1016/j.parco.2022.102920
intvolume: ' 111'
keyword:
- Artificial Intelligence
- Computer Graphics and Computer-Aided Design
- Computer Networks and Communications
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://www.sciencedirect.com/science/article/pii/S0167819122000242
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Parallel Computing
publication_identifier:
issn:
- 0167-8191
publication_status: published
publisher: Elsevier BV
quality_controlled: '1'
status: public
title: Towards electronic structure-based ab-initio molecular dynamics simulations
with hundreds of millions of atoms
type: journal_article
user_id: '75963'
volume: 111
year: '2022'
...
---
_id: '26746'
abstract:
- lang: eng
text: "Previous research in proof-carrying hardware has established the feasibility
and utility of the approach, and provided a concrete solution for employing it
for the certification of functional equivalence checking against a specification,
but fell short in connecting it to state-of-the-art formal verification insights,
methods and tools. Due to the immense complexity of modern circuits, and verification
challenges such as the state explosion problem for sequential circuits, this restriction
of readily-available verification solutions severely limited the applicability
of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the
PCH approach and current advances in formal hardware verification, provides methods
and tools to express and certify a wide range of circuit properties, both functional
and non-functional, and presents for the first time prototypes in which circuits
that are implemented on actual reconfigurable hardware are verified with PCH methods.
Using these results, designers can now apply PCH to establish trust in more complex
circuits, by using more diverse properties which they can express using modern,
efficient property specification techniques."
- lang: ger
text: "Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit
und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen
Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen,
Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund
der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der
Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung
sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem
größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen
PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden
und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite
von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale.
Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels
PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert
sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen
in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt
von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt
werden können."
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University; 2021.
apa: Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn University.
bibtex: '@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties
of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn
University}, author={Wiersema, Tobias}, year={2021} }'
chicago: 'Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
ieee: 'T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
mla: Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University, 2021.
short: T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
date_created: 2021-10-25T06:35:41Z
date_updated: 2022-01-06T06:57:26Z
ddc:
- '006'
department:
- _id: '78'
keyword:
- Proof-Carrying Hardware
- Formal Verification
- Sequential Circuits
- Non-Functional Properties
- Functional Properties
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800
oa: '1'
page: '293'
place: Paderborn
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication_status: published
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying
Hardware
type: dissertation
user_id: '3118'
year: '2021'
...
---
_id: '30907'
author:
- first_name: Alfonso
full_name: Rodriguez, Alfonso
last_name: Rodriguez
- first_name: Andres
full_name: Otero, Andres
last_name: Otero
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Eduardo
full_name: De la Torre, Eduardo
last_name: De la Torre
citation:
ama: Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs. IEEE Transactions on Computers. Published online 2021:1-1. doi:10.1109/tc.2021.3107196
apa: Rodriguez, A., Otero, A., Platzner, M., & De la Torre, E. (2021). Exploiting
Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing
in Reconfigurable FPGAs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2021.3107196
bibtex: '@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs}, DOI={10.1109/tc.2021.3107196},
journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and
Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and
Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }'
chicago: Rodriguez, Alfonso, Andres Otero, Marco Platzner, and Eduardo De la Torre.
“Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge
Computing in Reconfigurable FPGAs.” IEEE Transactions on Computers, 2021,
1–1. https://doi.org/10.1109/tc.2021.3107196.
ieee: 'A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based
Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable
FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196.'
mla: Rodriguez, Alfonso, et al. “Exploiting Hardware-Based Data-Parallel and Multithreading
Models for Smart Edge Computing in Reconfigurable FPGAs.” IEEE Transactions
on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2021,
pp. 1–1, doi:10.1109/tc.2021.3107196.
short: A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on
Computers (2021) 1–1.
date_created: 2022-04-18T10:03:16Z
date_updated: 2022-04-18T10:04:21Z
department:
- _id: '78'
doi: 10.1109/tc.2021.3107196
keyword:
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
page: 1-1
publication: IEEE Transactions on Computers
publication_identifier:
issn:
- 0018-9340
- 1557-9956
- 2326-3814
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart
Edge Computing in Reconfigurable FPGAs
type: journal_article
user_id: '398'
year: '2021'
...
---
_id: '45844'
abstract:
- lang: eng
text: "Abstract\r\n Abductive reasoning
is a non-monotonic formalism stemming from the work of Peirce. It describes the
process of deriving the most plausible explanations of known facts. Considering
the positive version, asking for sets of variables as explanations, we study,
besides the problem of wether there exists a set of explanations, two explanation
size limited variants of this reasoning problem (less than or equal to, and equal
to a given size bound). In this paper, we present a thorough two-dimensional classification
of these problems: the first dimension is regarding the parameterized complexity
under a wealth of different parameterizations, and the second dimension spans
through all possible Boolean fragments of these problems in Schaefer’s constraint
satisfaction framework with co-clones (T. J. Schaefer. The complexity of satisfiability
problems. In Proceedings of the 10th Annual ACM Symposium on Theory of Computing,
May 1–3, 1978, San Diego, California, USA, R.J. Lipton, W.A. Burkhard, W.J. Savitch,
E.P. Friedman, A.V. Aho eds, pp. 216–226. ACM, 1978). Thereby, we almost complete
the parameterized complexity classification program initiated by Fellows et al.
(The parameterized complexity of abduction. In Proceedings of the Twenty-Sixth
AAAI Conference on Articial Intelligence, July 22–26, 2012, Toronto, Ontario,
Canada, J. Homann, B. Selman eds. AAAI Press, 2012), partially building on the
results by Nordh and Zanuttini (What makes propositional abduction tractable.
Artificial Intelligence, 172, 1245–1284, 2008). In this process, we outline a
fine-grained analysis of the inherent parameterized intractability of these problems
and pinpoint their FPT parts. As the standard algebraic approach is not applicable
to our problems, we develop an alternative method that makes the algebraic tools
partially available again."
author:
- first_name: Yasir
full_name: Mahmood, Yasir
last_name: Mahmood
- first_name: Arne
full_name: Meier, Arne
last_name: Meier
- first_name: Johannes
full_name: Schmidt, Johannes
last_name: Schmidt
citation:
ama: Mahmood Y, Meier A, Schmidt J. Parameterized complexity of abduction in Schaefer’s
framework. Journal of Logic and Computation. 2021;31(1):266-296. doi:10.1093/logcom/exaa079
apa: Mahmood, Y., Meier, A., & Schmidt, J. (2021). Parameterized complexity
of abduction in Schaefer’s framework. Journal of Logic and Computation,
31(1), 266–296. https://doi.org/10.1093/logcom/exaa079
bibtex: '@article{Mahmood_Meier_Schmidt_2021, title={Parameterized complexity of
abduction in Schaefer’s framework}, volume={31}, DOI={10.1093/logcom/exaa079},
number={1}, journal={Journal of Logic and Computation}, publisher={Oxford University
Press (OUP)}, author={Mahmood, Yasir and Meier, Arne and Schmidt, Johannes}, year={2021},
pages={266–296} }'
chicago: 'Mahmood, Yasir, Arne Meier, and Johannes Schmidt. “Parameterized Complexity
of Abduction in Schaefer’s Framework.” Journal of Logic and Computation
31, no. 1 (2021): 266–96. https://doi.org/10.1093/logcom/exaa079.'
ieee: 'Y. Mahmood, A. Meier, and J. Schmidt, “Parameterized complexity of abduction
in Schaefer’s framework,” Journal of Logic and Computation, vol. 31, no.
1, pp. 266–296, 2021, doi: 10.1093/logcom/exaa079.'
mla: Mahmood, Yasir, et al. “Parameterized Complexity of Abduction in Schaefer’s
Framework.” Journal of Logic and Computation, vol. 31, no. 1, Oxford University
Press (OUP), 2021, pp. 266–96, doi:10.1093/logcom/exaa079.
short: Y. Mahmood, A. Meier, J. Schmidt, Journal of Logic and Computation 31 (2021)
266–296.
date_created: 2023-07-03T11:35:23Z
date_updated: 2024-06-04T16:03:14Z
department:
- _id: '574'
doi: 10.1093/logcom/exaa079
extern: '1'
intvolume: ' 31'
issue: '1'
keyword:
- Logic
- Hardware and Architecture
- Arts and Humanities (miscellaneous)
- Software
- Theoretical Computer Science
language:
- iso: eng
page: 266-296
publication: Journal of Logic and Computation
publication_identifier:
issn:
- 0955-792X
- 1465-363X
publication_status: published
publisher: Oxford University Press (OUP)
status: public
title: Parameterized complexity of abduction in Schaefer’s framework
type: journal_article
user_id: '99353'
volume: 31
year: '2021'
...
---
_id: '27841'
abstract:
- lang: eng
text: Verification of software and processor hardware usually proceeds separately,
software analysis relying on the correctness of processors executing machine instructions.
This assumption is valid as long as the software runs on standard CPUs that have
been extensively validated and are in wide use. However, for processors exploiting
custom instruction set extensions to meet performance and energy constraints the
validation might be less extensive, challenging the correctness assumption. In
this paper we present a novel formal approach for hardware/software co-verification
targeting processors with custom instruction set extensions. We detail two different
approaches for checking whether the hardware fulfills the requirements expected
by the software analysis. The approaches are designed to explore a trade-off between
generality of the verification and computational effort. Then, we describe the
integration of software and hardware analyses for both techniques and describe
a fully automated tool chain implementing the approaches. Finally, we demonstrate
and compare the two approaches on example source code with custom instructions,
using state-of-the-art software analysis and hardware verification techniques.
author:
- first_name: Marie-Christine
full_name: Jakobs, Marie-Christine
last_name: Jakobs
- first_name: Felix
full_name: Pauck, Felix
id: '22398'
last_name: Pauck
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware
Co-Verification for Custom Instruction Set Processors. IEEE Access. Published
online 2021. doi:10.1109/ACCESS.2021.3131213
apa: Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021).
Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE
Access. https://doi.org/10.1109/ACCESS.2021.3131213
bibtex: '@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware
Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213},
journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck,
Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021}
}'
chicago: Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and
Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set
Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213.
ieee: 'M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware
Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021,
doi: 10.1109/ACCESS.2021.3131213.'
mla: Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom
Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213.
short: M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access
(2021).
date_created: 2021-11-25T14:12:22Z
date_updated: 2023-01-18T08:34:50Z
department:
- _id: '78'
doi: 10.1109/ACCESS.2021.3131213
funded_apc: '1'
keyword:
- Software Analysis
- Abstract Interpretation
- Custom Instruction
- Hardware Verification
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication: IEEE Access
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Software/Hardware Co-Verification for Custom Instruction Set Processors
type: journal_article
user_id: '22398'
year: '2021'
...
---
_id: '17358'
abstract:
- lang: eng
text: 'Approximate circuits trade-off computational accuracy against improvements
in hardware area, delay, or energy consumption. IP core vendors who wish to create
such circuits need to convince consumers of the resulting approximation quality.
As a solution we propose proof-carrying approximate circuits: The vendor creates
an approximate IP core together with a certificate that proves the approximation
quality. The proof certificate is bundled with the approximate IP core and sent
off to the consumer. The consumer can formally verify the approximation quality
of the IP core at a fraction of the typical computational cost for formal verification.
In this paper, we first make the case for proof-carrying approximate circuits
and then demonstrate the feasibility of the approach by a set of synthesis experiments
using an exemplary approximation framework.'
article_type: original
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE
Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088.
doi:10.1109/TVLSI.2020.3008061
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate
Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9),
2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061
bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate
Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061},
number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems},
publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner,
Marco}, year={2020}, pages={2084–2088} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems
28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.'
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate
Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol.
28, no. 9, pp. 2084–2088, 2020.
mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE
Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE,
2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.
short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large
Scale Integration Systems 28 (2020) 2084–2088.
date_created: 2020-07-06T11:21:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
doi: 10.1109/TVLSI.2020.3008061
funded_apc: '1'
intvolume: ' 28'
issue: '9'
keyword:
- Approximate circuit synthesis
- approximate computing
- error metrics
- formal verification
- proof-carrying hardware
language:
- iso: eng
page: 2084 - 2088
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: IEEE Transactions On Very Large Scale Integration Systems
publication_identifier:
eissn:
- 1557-9999
issn:
- 1063-8210
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Proof-carrying Approximate Circuits
type: journal_article
user_id: '49051'
volume: 28
year: '2020'
...
---
_id: '1097'
author:
- first_name: Felix Paul
full_name: Jentzsch, Felix Paul
last_name: Jentzsch
citation:
ama: Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security
Monitors. Universität Paderborn; 2018.
apa: Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn.
bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with
Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch,
Felix Paul}, year={2018} }'
chicago: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
ieee: F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
mla: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security
Monitors, Universität Paderborn, 2018.
date_created: 2018-01-15T16:48:05Z
date_updated: 2022-01-06T06:50:54Z
department:
- _id: '78'
keyword:
- Approximate Computing
- Proof-Carrying Hardware
- Formal Verification
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: Enforcing IP Core Connection Properties with Verifiable Security Monitors
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '10676'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International
Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
In 2017 International Conference on Field Programmable Technology (ICFPT)
(pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor},
DOI={10.1109/FPT.2017.8280144},
booktitle={2017 International Conference on Field Programmable Technology (ICFPT)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218}
}'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization
of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”
In 2017 International Conference on Field Programmable Technology (ICFPT),
215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International
Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.'
mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings
for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference
on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field
Programmable Technology (ICFPT), 2017, pp. 215–218.'
date_created: 2019-07-10T11:22:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPT.2017.8280144
keyword:
- Linux
- cache storage
- microprocessor chips
- multiprocessing systems
- LEON3-Linux based multicore processor
- MiBench suite
- block sizes
- cache adaptation
- evolvable caches
- memory-to-cache-index mapping function
- processor caches
- reconfigurable cache mapping optimization
- reconfigurable hardware technology
- replacement strategies
- standard Linux OS
- time a complete hardware implementation
- Hardware
- Indexes
- Linux
- Measurement
- Multicore processing
- Optimization
- Training
language:
- iso: eng
page: 215-218
publication: 2017 International Conference on Field Programmable Technology (ICFPT)
status: public
title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based
multi-core processor'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '10780'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Philipp
full_name: Hübner, Philipp
last_name: Hübner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: 'Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness
as design approach for visual sensor nodes. In: 12th International Symposium
on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8.
doi:10.1109/ReCoSoC.2017.8016147'
apa: Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational
self-awareness as design approach for visual sensor nodes. In 12th International
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
(pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147
bibtex: '@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational
self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147},
booktitle={12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and
Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }'
chicago: Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner.
“Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In
12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip
(ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.
ieee: Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness
as design approach for visual sensor nodes,” in 12th International Symposium
on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp.
1–8.
mla: Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach
for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric
Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.
short: 'Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International
Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017,
pp. 1–8.'
date_created: 2019-07-10T12:13:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ReCoSoC.2017.8016147
keyword:
- embedded systems
- image sensors
- power aware computing
- wireless sensor networks
- Zynq-based VSN node prototype
- computational self-awareness
- design approach
- platform levels
- power consumption
- visual sensor networks
- visual sensor nodes
- Cameras
- Hardware
- Middleware
- Multicore processing
- Operating systems
- Runtime
- Reconfigurable platforms
- distributed embedded systems
- performance-resource trade-off
- self-awareness
- visual sensor nodes
language:
- iso: eng
page: 1-8
publication: 12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)
status: public
title: Computational self-awareness as design approach for visual sensor nodes
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '15873'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Florian
full_name: Kraus, Florian
last_name: Kraus
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based
acceleration of high density myoelectric signal processing. In: 2015 International
Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312'
apa: 'Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., &
Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal
processing. In 2015 International Conference on ReConFigurable Computing and
FPGAs (ReConFig). Mexiko City, Mexiko: IEEE. https://doi.org/10.1109/reconfig.2015.7393312'
bibtex: '@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016,
title={FPGA-based acceleration of high density myoelectric signal processing},
DOI={10.1109/reconfig.2015.7393312},
booktitle={2015 International Conference on ReConFigurable Computing and FPGAs
(ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas
and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner,
Marco}, year={2016} }'
chicago: Boschmann, Alexander, Andreas Agne, Linus Matthias Witschen, Georg Thombansen,
Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric
Signal Processing.” In 2015 International Conference on ReConFigurable Computing
and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.
ieee: A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner,
“FPGA-based acceleration of high density myoelectric signal processing,” in 2015
International Conference on ReConFigurable Computing and FPGAs (ReConFig),
Mexiko City, Mexiko, 2016.
mla: Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric
Signal Processing.” 2015 International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.
short: 'A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner,
in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig),
IEEE, 2016.'
conference:
location: Mexiko City, Mexiko
name: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
date_created: 2020-02-11T07:48:56Z
date_updated: 2022-01-06T06:52:38Z
department:
- _id: '78'
doi: 10.1109/reconfig.2015.7393312
keyword:
- Electromyography
- Feature extraction
- Delays
- Hardware Pattern recognition
- Prosthetics
- High definition video
language:
- iso: eng
publication: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
publication_identifier:
isbn:
- '9781467394062'
publication_status: published
publisher: IEEE
status: public
title: FPGA-based acceleration of high density myoelectric signal processing
type: conference
user_id: '49051'
year: '2016'
...
---
_id: '10779'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks
scheduling and allocation. In: 25th International Conference on Field Programmable
Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994'
apa: Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time
hardware tasks scheduling and allocation. In 25th International Conference
on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994
bibtex: '@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard
real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994},
booktitle={25th International Conference on Field Programmable Logic and Applications
(FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar
and Khouas, Abdelhakim}, year={2015} }'
chicago: Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective
Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International
Conference on Field Programmable Logic and Applications (FPL). Imperial College,
2015. https://doi.org/10.1109/FPL.2015.7293994.
ieee: Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware
tasks scheduling and allocation,” in 25th International Conference on Field
Programmable Logic and Applications (FPL), 2015.
mla: Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling
and Allocation.” 25th International Conference on Field Programmable Logic
and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.
short: 'Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on
Field Programmable Logic and Applications (FPL), Imperial College, 2015.'
date_created: 2019-07-10T12:11:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPL.2015.7293994
extern: '1'
keyword:
- embedded systems
- field programmable gate arrays
- operating systems (computers)
- scheduling
- μC/OS-II
- FPGAs
- OS foundation
- SafeRTOS
- Xenomai
- chip utilization ration
- complex time constraints
- embedded systems
- hard real-time hardware task allocation
- hard real-time hardware task scheduling
- hardware-software real-time operating systems
- partially reconfigurable field-programmable gate arrays
- resource constraints
- safety-critical RTOS
- Field programmable gate arrays
- Hardware
- Job shop scheduling
- Real-time systems
- Shape
- Software
language:
- iso: eng
publication: 25th International Conference on Field Programmable Logic and Applications
(FPL)
publication_identifier:
issn:
- 1946-147X
publisher: Imperial College
status: public
title: Over effective hard real-time hardware tasks scheduling and allocation
type: conference
user_id: '398'
year: '2015'
...
---
_id: '39479'
author:
- first_name: Fábio
full_name: Vidor, Fábio
last_name: Vidor
- first_name: Thorsten
full_name: Meyers, Thorsten
last_name: Meyers
- first_name: Ulrich
full_name: Hilleringmann, Ulrich
id: '20179'
last_name: Hilleringmann
citation:
ama: 'Vidor F, Meyers T, Hilleringmann U. Flexible Electronics: Integration Processes
for Organic and Inorganic Semiconductor-Based Thin-Film Transistors. Electronics.
2015;4(3):480-506. doi:10.3390/electronics4030480'
apa: 'Vidor, F., Meyers, T., & Hilleringmann, U. (2015). Flexible Electronics:
Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film
Transistors. Electronics, 4(3), 480–506. https://doi.org/10.3390/electronics4030480'
bibtex: '@article{Vidor_Meyers_Hilleringmann_2015, title={Flexible Electronics:
Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film
Transistors}, volume={4}, DOI={10.3390/electronics4030480},
number={3}, journal={Electronics}, publisher={MDPI AG}, author={Vidor, Fábio and
Meyers, Thorsten and Hilleringmann, Ulrich}, year={2015}, pages={480–506} }'
chicago: 'Vidor, Fábio, Thorsten Meyers, and Ulrich Hilleringmann. “Flexible Electronics:
Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film
Transistors.” Electronics 4, no. 3 (2015): 480–506. https://doi.org/10.3390/electronics4030480.'
ieee: 'F. Vidor, T. Meyers, and U. Hilleringmann, “Flexible Electronics: Integration
Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors,”
Electronics, vol. 4, no. 3, pp. 480–506, 2015, doi: 10.3390/electronics4030480.'
mla: 'Vidor, Fábio, et al. “Flexible Electronics: Integration Processes for Organic
and Inorganic Semiconductor-Based Thin-Film Transistors.” Electronics,
vol. 4, no. 3, MDPI AG, 2015, pp. 480–506, doi:10.3390/electronics4030480.'
short: F. Vidor, T. Meyers, U. Hilleringmann, Electronics 4 (2015) 480–506.
date_created: 2023-01-24T11:23:57Z
date_updated: 2023-03-21T10:16:23Z
department:
- _id: '59'
doi: 10.3390/electronics4030480
intvolume: ' 4'
issue: '3'
keyword:
- Electrical and Electronic Engineering
- Computer Networks and Communications
- Hardware and Architecture
- Signal Processing
- Control and Systems Engineering
language:
- iso: eng
page: 480-506
publication: Electronics
publication_identifier:
issn:
- 2079-9292
publication_status: published
publisher: MDPI AG
status: public
title: 'Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based
Thin-Film Transistors'
type: journal_article
user_id: '20179'
volume: 4
year: '2015'
...
---
_id: '10674'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance
monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437},
booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4}
}'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure
for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for
performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on
Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.
mla: Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring
on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic
and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL), 2014, pp. 1–4.'
date_created: 2019-07-10T11:18:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPL.2014.6927437
keyword:
- Linux
- hardware-software codesign
- multiprocessing systems
- parallel processing
- LEON3 multicore platform
- Linux kernel
- PMU
- hardware counters
- hardware-software infrastructure
- high performance embedded computing
- perf_event
- performance monitoring unit
- Computer architecture
- Hardware
- Monitoring
- Phasor measurement units
- Radiation detectors
- Registers
- Software
language:
- iso: eng
page: 1-4
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL)
status: public
title: A hardware/software infrastructure for performance monitoring on LEON3 multicore
platforms
type: conference
user_id: '3118'
year: '2014'
...