[{"language":[{"iso":"eng"}],"_id":"36994","publisher":"IEEE","doi":"10.1109/SOCC.2012.6398362","user_id":"5786","year":"2012","title":"Mutation-Analysis Driven Functional Verification of a Soft Microprocessor","status":"public","author":[{"last_name":"Xie","first_name":"Tao ","full_name":"Xie, Tao "},{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"},{"full_name":"Letombe, Florian","first_name":"Florian","last_name":"Letombe"}],"publication_identifier":{"eisbn":["978-1-4673-1295-0"]},"date_updated":"2023-01-17T08:46:29Z","place":" Niagara Falls, NY, USA ","date_created":"2023-01-17T08:46:14Z","keyword":["Analytical models","Hardware design languages","Microprocessors","Cost function","Data models","Search problems","IP networks"],"type":"conference","department":[{"_id":"672"}],"publication":"Proceedings of SOCC2012","citation":{"mla":"Xie, Tao, et al. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” <i>Proceedings of SOCC2012</i>, IEEE, 2012, doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","bibtex":"@inproceedings{Xie_Müller_Letombe_2012, place={ Niagara Falls, NY, USA }, title={Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}, DOI={<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>}, booktitle={Proceedings of SOCC2012}, publisher={IEEE}, author={Xie, Tao  and Müller, Wolfgang and Letombe, Florian}, year={2012} }","ama":"Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. In: <i>Proceedings of SOCC2012</i>. IEEE; 2012. doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>","ieee":"T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor,” 2012, doi: <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","apa":"Xie, T., Müller, W., &#38; Letombe, F. (2012). Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. <i>Proceedings of SOCC2012</i>. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>","chicago":"Xie, Tao , Wolfgang Müller, and Florian Letombe. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” In <i>Proceedings of SOCC2012</i>.  Niagara Falls, NY, USA : IEEE, 2012. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>.","short":"T. Xie, W. Müller, F. Letombe, in: Proceedings of SOCC2012, IEEE,  Niagara Falls, NY, USA , 2012."},"abstract":[{"lang":"eng","text":"This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP."}]},{"date_updated":"2025-02-26T14:44:15Z","publication_identifier":{"isbn":["978-1-4577-1048-3"]},"author":[{"last_name":"Xie","first_name":"Tao","full_name":"Xie, Tao"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"last_name":"Letombe","first_name":"Florian","full_name":"Letombe, Florian"}],"year":"2011","title":"HDL-Mutation Based Simulation Data Generation by Propagation Guided Search","status":"public","user_id":"5786","doi":"10.1109/DSD.2011.83","_id":"37002","language":[{"iso":"eng"}],"publisher":"IEEE","abstract":[{"text":"HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.","lang":"eng"}],"citation":{"bibtex":"@inproceedings{Xie_Müller_Letombe_2011, place={Oulu, Finnland}, title={HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}, DOI={<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>}, booktitle={Proceedings of Euromicro DSD 2011}, publisher={IEEE}, author={Xie, Tao and Müller, Wolfgang and Letombe, Florian}, year={2011} }","short":"T. Xie, W. Müller, F. Letombe, in: Proceedings of Euromicro DSD 2011, IEEE, Oulu, Finnland, 2011.","ama":"Xie T, Müller W, Letombe F. HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. In: <i>Proceedings of Euromicro DSD 2011</i>. IEEE; 2011. doi:<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>","chicago":"Xie, Tao, Wolfgang Müller, and Florian Letombe. “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.” In <i>Proceedings of Euromicro DSD 2011</i>. Oulu, Finnland: IEEE, 2011. <a href=\"https://doi.org/10.1109/DSD.2011.83\">https://doi.org/10.1109/DSD.2011.83</a>.","ieee":"T. Xie, W. Müller, and F. Letombe, “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search,” 2011, doi: <a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>.","mla":"Xie, Tao, et al. “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.” <i>Proceedings of Euromicro DSD 2011</i>, IEEE, 2011, doi:<a href=\"https://doi.org/10.1109/DSD.2011.83\">10.1109/DSD.2011.83</a>.","apa":"Xie, T., Müller, W., &#38; Letombe, F. (2011). HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. <i>Proceedings of Euromicro DSD 2011</i>. <a href=\"https://doi.org/10.1109/DSD.2011.83\">https://doi.org/10.1109/DSD.2011.83</a>"},"publication":"Proceedings of Euromicro DSD 2011","department":[{"_id":"672"}],"type":"conference","keyword":["Hardware design languages","Cost function","Computational modeling","Fault detection","Data models","Analytical models","Testing"],"date_created":"2023-01-17T09:02:48Z","place":"Oulu, Finnland"},{"language":[{"iso":"eng"}],"_id":"38107","doi":"10.1109/ISoLA.2006.37","user_id":"5786","conference":{"location":"Paphos, Cyprus"},"author":[{"full_name":"Großmann, Jürgen","last_name":"Großmann","first_name":"Jürgen"},{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"}],"publication_identifier":{"isbn":["978-0-7695-3071-0"]},"status":"public","year":"2006","title":"A Formal Behavioral Semantics for TestML","date_updated":"2023-01-23T12:06:26Z","place":"Paphos, Cyprus","date_created":"2023-01-23T12:00:06Z","department":[{"_id":"672"}],"keyword":["System testing","Software testing","Automotive engineering","Automatic testing","Machinery production industries","Protocols","Hardware design languages","Samarium","XML","Computer industry"],"type":"conference","citation":{"bibtex":"@inproceedings{Großmann_Müller_2006, place={Paphos, Cyprus}, title={A Formal Behavioral Semantics for TestML}, DOI={<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>}, booktitle={Proc. of ISOLA 06}, author={Großmann, Jürgen and Müller, Wolfgang}, year={2006} }","ama":"Großmann J, Müller W. A Formal Behavioral Semantics for TestML. In: <i>Proc. of ISOLA 06</i>. ; 2006. doi:<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>","mla":"Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.” <i>Proc. of ISOLA 06</i>, 2006, doi:<a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>.","short":"J. Großmann, W. Müller, in: Proc. of ISOLA 06, Paphos, Cyprus, 2006.","chicago":"Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.” In <i>Proc. of ISOLA 06</i>. Paphos, Cyprus, 2006. <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">https://doi.org/10.1109/ISoLA.2006.37</a>.","ieee":"J. Großmann and W. Müller, “A Formal Behavioral Semantics for TestML,” Paphos, Cyprus, 2006, doi: <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">10.1109/ISoLA.2006.37</a>.","apa":"Großmann, J., &#38; Müller, W. (2006). A Formal Behavioral Semantics for TestML. <i>Proc. of ISOLA 06</i>. <a href=\"https://doi.org/10.1109/ISoLA.2006.37\">https://doi.org/10.1109/ISoLA.2006.37</a>"},"publication":"Proc. of ISOLA 06","abstract":[{"lang":"eng","text":"TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML."}]},{"date_updated":"2023-01-24T10:39:38Z","status":"public","year":"2001","title":"The Simulation Semantics of SystemC","conference":{"name":" Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001"},"author":[{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"first_name":"Jürgen","last_name":"Ruf","full_name":"Ruf, Jürgen"},{"last_name":"Hoffmann","first_name":"D. W.","full_name":"Hoffmann, D. W."},{"last_name":"Gerlach","first_name":"Joachim","full_name":"Gerlach, Joachim"},{"full_name":"Kropf, Thomas","last_name":"Kropf","first_name":"Thomas"},{"full_name":"Rosenstiehl, W.","first_name":"W.","last_name":"Rosenstiehl"}],"publication_identifier":{"isbn":["0-7695-0993-2"]},"doi":"10.1109/DATE.2001.915002","user_id":"5786","language":[{"iso":"eng"}],"_id":"39421","publisher":"IEEE","abstract":[{"lang":"eng","text":"We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL."}],"publication":"Proceedings of the Design, Automation, and Test in Europe (DATE’01)","citation":{"mla":"Müller, Wolfgang, et al. “The Simulation Semantics of SystemC.” <i>Proceedings of the Design, Automation, and Test in Europe (DATE’01)</i>, IEEE, 2001, doi:<a href=\"https://doi.org/10.1109/DATE.2001.915002\">10.1109/DATE.2001.915002</a>.","ama":"Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation Semantics of SystemC. In: <i>Proceedings of the Design, Automation, and Test in Europe (DATE’01)</i>. IEEE; 2001. doi:<a href=\"https://doi.org/10.1109/DATE.2001.915002\">10.1109/DATE.2001.915002</a>","bibtex":"@inproceedings{Müller_Ruf_Hoffmann_Gerlach_Kropf_Rosenstiehl_2001, place={Munich, Germany }, title={The Simulation Semantics of SystemC}, DOI={<a href=\"https://doi.org/10.1109/DATE.2001.915002\">10.1109/DATE.2001.915002</a>}, booktitle={Proceedings of the Design, Automation, and Test in Europe (DATE’01)}, publisher={IEEE}, author={Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W. and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}, year={2001} }","apa":"Müller, W., Ruf, J., Hoffmann, D. W., Gerlach, J., Kropf, T., &#38; Rosenstiehl, W. (2001). The Simulation Semantics of SystemC. <i>Proceedings of the Design, Automation, and Test in Europe (DATE’01)</i>.  Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001. <a href=\"https://doi.org/10.1109/DATE.2001.915002\">https://doi.org/10.1109/DATE.2001.915002</a>","ieee":"W. Müller, J. Ruf, D. W. Hoffmann, J. Gerlach, T. Kropf, and W. Rosenstiehl, “The Simulation Semantics of SystemC,” presented at the  Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, doi: <a href=\"https://doi.org/10.1109/DATE.2001.915002\">10.1109/DATE.2001.915002</a>.","chicago":"Müller, Wolfgang, Jürgen Ruf, D. W. Hoffmann, Joachim Gerlach, Thomas Kropf, and W. Rosenstiehl. “The Simulation Semantics of SystemC.” In <i>Proceedings of the Design, Automation, and Test in Europe (DATE’01)</i>. Munich, Germany : IEEE, 2001. <a href=\"https://doi.org/10.1109/DATE.2001.915002\">https://doi.org/10.1109/DATE.2001.915002</a>.","short":"W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl, in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE, Munich, Germany , 2001."},"keyword":["Yarn","Formal verification","Kernel","Hardware design languages","Electronic design automation and methodology","Algebra","Computational modeling","Logic functions","Computer languages","Clocks"],"type":"conference","department":[{"_id":"672"}],"place":"Munich, Germany ","date_created":"2023-01-24T10:39:33Z"}]