---
_id: '36994'
abstract:
- lang: eng
text: This paper proposes a quality driven, simulation based approach to functional
design verification, which applies mainly to IP-level HDL designs with well specified
test instruction format and is evaluated on a soft microprocessor core MB-LITE
[5]. The approach utilizes mutation analysis as the quality metric to steer an
automated simulation data generation process. It leads to a simulation flow with
two phases towards an enhanced mutation analysis result. First in a random simulation
phase, an in-loop heuristics is deployed and adjusts dynamically the test probability
distribution so as to improve the coverage efficiency. Next, for each remaining
hard-to-kill mutant, a search heuristics on test input space is developed to iteratively
locate a target test, using a specific objective cost function for the goal of
killing HDL mutant. The effectiveness of this integrated two-phase simulation
flow is demonstrated by the results with the MB-LITE microprocessor IP.
author:
- first_name: 'Tao '
full_name: 'Xie, Tao '
last_name: Xie
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Florian
full_name: Letombe, Florian
last_name: Letombe
citation:
ama: 'Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification
of a Soft Microprocessor. In: Proceedings of SOCC2012. IEEE; 2012. doi:10.1109/SOCC.2012.6398362'
apa: Xie, T., Müller, W., & Letombe, F. (2012). Mutation-Analysis Driven Functional
Verification of a Soft Microprocessor. Proceedings of SOCC2012. https://doi.org/10.1109/SOCC.2012.6398362
bibtex: '@inproceedings{Xie_Müller_Letombe_2012, place={ Niagara Falls, NY, USA
}, title={Mutation-Analysis Driven Functional Verification of a Soft Microprocessor},
DOI={10.1109/SOCC.2012.6398362},
booktitle={Proceedings of SOCC2012}, publisher={IEEE}, author={Xie, Tao and Müller,
Wolfgang and Letombe, Florian}, year={2012} }'
chicago: 'Xie, Tao , Wolfgang Müller, and Florian Letombe. “Mutation-Analysis Driven
Functional Verification of a Soft Microprocessor.” In Proceedings of SOCC2012. Niagara
Falls, NY, USA : IEEE, 2012. https://doi.org/10.1109/SOCC.2012.6398362.'
ieee: 'T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification
of a Soft Microprocessor,” 2012, doi: 10.1109/SOCC.2012.6398362.'
mla: Xie, Tao, et al. “Mutation-Analysis Driven Functional Verification of a Soft
Microprocessor.” Proceedings of SOCC2012, IEEE, 2012, doi:10.1109/SOCC.2012.6398362.
short: 'T. Xie, W. Müller, F. Letombe, in: Proceedings of SOCC2012, IEEE, Niagara
Falls, NY, USA , 2012.'
date_created: 2023-01-17T08:46:14Z
date_updated: 2023-01-17T08:46:29Z
department:
- _id: '672'
doi: 10.1109/SOCC.2012.6398362
keyword:
- Analytical models
- Hardware design languages
- Microprocessors
- Cost function
- Data models
- Search problems
- IP networks
language:
- iso: eng
place: ' Niagara Falls, NY, USA '
publication: Proceedings of SOCC2012
publication_identifier:
eisbn:
- 978-1-4673-1295-0
publisher: IEEE
status: public
title: Mutation-Analysis Driven Functional Verification of a Soft Microprocessor
type: conference
user_id: '5786'
year: '2012'
...
---
_id: '37002'
abstract:
- lang: eng
text: HDL-mutation based fault injection and analysis is considered as an important
coverage metric for measuring the quality of design simulation processes [20,
3, 1, 2]. In this work, we try to solve the problem of automatic simulation data
generation targeting HDL mutation faults. We follow a search based approach and
eliminate the need for symbolic execution and mathematical constraint solving
from existing work. An objective cost function is defined on the test input space
and serves the guidance of search for fault-detecting test data. This is done
by first mapping the simulation traces under a test onto a control and data flow
graph structure which is extracted from the design. Then the progress of fault
detection can be measured quantitatively on this graph to be the cost value. By
minimizing this cost we approach the target test data. The effectiveness of the
cost function is investigated under an example neighborhood search scheme. Case
study with a floating point arithmetic IP design has shown that the cost function
is able to guide effectively the search procedure towards a fault-detecting test.
The cost calculation time as the search overhead was also observed to be minor
compared to the actual design simulation time.
author:
- first_name: Tao
full_name: Xie, Tao
last_name: Xie
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Florian
full_name: Letombe, Florian
last_name: Letombe
citation:
ama: 'Xie T, Müller W, Letombe F. HDL-Mutation Based Simulation Data Generation
by Propagation Guided Search. In: Proceedings of Euromicro DSD 2011. IEEE;
2011. doi:10.1109/DSD.2011.83'
apa: Xie, T., Müller, W., & Letombe, F. (2011). HDL-Mutation Based Simulation
Data Generation by Propagation Guided Search. Proceedings of Euromicro DSD
2011. https://doi.org/10.1109/DSD.2011.83
bibtex: '@inproceedings{Xie_Müller_Letombe_2011, place={Oulu, Finnland}, title={HDL-Mutation
Based Simulation Data Generation by Propagation Guided Search}, DOI={10.1109/DSD.2011.83},
booktitle={Proceedings of Euromicro DSD 2011}, publisher={IEEE}, author={Xie,
Tao and Müller, Wolfgang and Letombe, Florian}, year={2011} }'
chicago: 'Xie, Tao, Wolfgang Müller, and Florian Letombe. “HDL-Mutation Based Simulation
Data Generation by Propagation Guided Search.” In Proceedings of Euromicro
DSD 2011. Oulu, Finnland: IEEE, 2011. https://doi.org/10.1109/DSD.2011.83.'
ieee: 'T. Xie, W. Müller, and F. Letombe, “HDL-Mutation Based Simulation Data Generation
by Propagation Guided Search,” 2011, doi: 10.1109/DSD.2011.83.'
mla: Xie, Tao, et al. “HDL-Mutation Based Simulation Data Generation by Propagation
Guided Search.” Proceedings of Euromicro DSD 2011, IEEE, 2011, doi:10.1109/DSD.2011.83.
short: 'T. Xie, W. Müller, F. Letombe, in: Proceedings of Euromicro DSD 2011, IEEE,
Oulu, Finnland, 2011.'
date_created: 2023-01-17T09:02:48Z
date_updated: 2025-02-26T14:44:15Z
department:
- _id: '672'
doi: 10.1109/DSD.2011.83
keyword:
- Hardware design languages
- Cost function
- Computational modeling
- Fault detection
- Data models
- Analytical models
- Testing
language:
- iso: eng
place: Oulu, Finnland
publication: Proceedings of Euromicro DSD 2011
publication_identifier:
isbn:
- 978-1-4577-1048-3
publisher: IEEE
status: public
title: HDL-Mutation Based Simulation Data Generation by Propagation Guided Search
type: conference
user_id: '5786'
year: '2011'
...
---
_id: '38107'
abstract:
- lang: eng
text: TestML is an XML-based language for the exchange of test descriptions in automotive
systems design and mainly introduced through the structural definition of an XML
schema as an independent exchange format for existing tools and methods covering
a wide range of different test technologies. In this paper, we present a rigorous
formal behavioral semantics for TestML by means of Abstract State Machines (ASMs).
Our semantics is a concise, unambiguous, high-level specification for TestML-based
implementations and serves as a basis to define exact and well-defined mappings
between existing test languages and TestML.
author:
- first_name: Jürgen
full_name: Großmann, Jürgen
last_name: Großmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Großmann J, Müller W. A Formal Behavioral Semantics for TestML. In: Proc.
of ISOLA 06. ; 2006. doi:10.1109/ISoLA.2006.37'
apa: Großmann, J., & Müller, W. (2006). A Formal Behavioral Semantics for TestML.
Proc. of ISOLA 06. https://doi.org/10.1109/ISoLA.2006.37
bibtex: '@inproceedings{Großmann_Müller_2006, place={Paphos, Cyprus}, title={A Formal
Behavioral Semantics for TestML}, DOI={10.1109/ISoLA.2006.37},
booktitle={Proc. of ISOLA 06}, author={Großmann, Jürgen and Müller, Wolfgang},
year={2006} }'
chicago: Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for
TestML.” In Proc. of ISOLA 06. Paphos, Cyprus, 2006. https://doi.org/10.1109/ISoLA.2006.37.
ieee: 'J. Großmann and W. Müller, “A Formal Behavioral Semantics for TestML,” Paphos,
Cyprus, 2006, doi: 10.1109/ISoLA.2006.37.'
mla: Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.”
Proc. of ISOLA 06, 2006, doi:10.1109/ISoLA.2006.37.
short: 'J. Großmann, W. Müller, in: Proc. of ISOLA 06, Paphos, Cyprus, 2006.'
conference:
location: Paphos, Cyprus
date_created: 2023-01-23T12:00:06Z
date_updated: 2023-01-23T12:06:26Z
department:
- _id: '672'
doi: 10.1109/ISoLA.2006.37
keyword:
- System testing
- Software testing
- Automotive engineering
- Automatic testing
- Machinery production industries
- Protocols
- Hardware design languages
- Samarium
- XML
- Computer industry
language:
- iso: eng
place: Paphos, Cyprus
publication: Proc. of ISOLA 06
publication_identifier:
isbn:
- 978-0-7695-3071-0
status: public
title: A Formal Behavioral Semantics for TestML
type: conference
user_id: '5786'
year: '2006'
...
---
_id: '39421'
abstract:
- lang: eng
text: We present a rigorous but transparent semantics definition of SystemC that
covers method, thread, and clocked thread behavior as well as their interaction
with the simulation kernel process. The semantics includes watching statements,
signal assignment, and wait statements as they are introduced in SystemC V1.O.
We present our definition in form of distributed Abstract State Machines (ASMs)
rules reflecting the view given in the SystemC User's Manual and the reference
implementation. We mainly see our formal semantics as a concise, unambiguous,
high-level specification for SystemC-based implementations and for standardization.
Additionally, it can be used as a sound basis to investigate SystemC interoperability
with Verilog and VHDL.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Jürgen
full_name: Ruf, Jürgen
last_name: Ruf
- first_name: D. W.
full_name: Hoffmann, D. W.
last_name: Hoffmann
- first_name: Joachim
full_name: Gerlach, Joachim
last_name: Gerlach
- first_name: Thomas
full_name: Kropf, Thomas
last_name: Kropf
- first_name: W.
full_name: Rosenstiehl, W.
last_name: Rosenstiehl
citation:
ama: 'Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation
Semantics of SystemC. In: Proceedings of the Design, Automation, and Test in
Europe (DATE’01). IEEE; 2001. doi:10.1109/DATE.2001.915002'
apa: Müller, W., Ruf, J., Hoffmann, D. W., Gerlach, J., Kropf, T., & Rosenstiehl,
W. (2001). The Simulation Semantics of SystemC. Proceedings of the Design,
Automation, and Test in Europe (DATE’01). Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001. https://doi.org/10.1109/DATE.2001.915002
bibtex: '@inproceedings{Müller_Ruf_Hoffmann_Gerlach_Kropf_Rosenstiehl_2001, place={Munich,
Germany }, title={The Simulation Semantics of SystemC}, DOI={10.1109/DATE.2001.915002},
booktitle={Proceedings of the Design, Automation, and Test in Europe (DATE’01)},
publisher={IEEE}, author={Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W.
and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}, year={2001} }'
chicago: 'Müller, Wolfgang, Jürgen Ruf, D. W. Hoffmann, Joachim Gerlach, Thomas
Kropf, and W. Rosenstiehl. “The Simulation Semantics of SystemC.” In Proceedings
of the Design, Automation, and Test in Europe (DATE’01). Munich, Germany :
IEEE, 2001. https://doi.org/10.1109/DATE.2001.915002.'
ieee: 'W. Müller, J. Ruf, D. W. Hoffmann, J. Gerlach, T. Kropf, and W. Rosenstiehl,
“The Simulation Semantics of SystemC,” presented at the Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001, 2001, doi: 10.1109/DATE.2001.915002.'
mla: Müller, Wolfgang, et al. “The Simulation Semantics of SystemC.” Proceedings
of the Design, Automation, and Test in Europe (DATE’01), IEEE, 2001, doi:10.1109/DATE.2001.915002.
short: 'W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl,
in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE,
Munich, Germany , 2001.'
conference:
name: ' Proceedings Design, Automation and Test in Europe. Conference and Exhibition
2001'
date_created: 2023-01-24T10:39:33Z
date_updated: 2023-01-24T10:39:38Z
department:
- _id: '672'
doi: 10.1109/DATE.2001.915002
keyword:
- Yarn
- Formal verification
- Kernel
- Hardware design languages
- Electronic design automation and methodology
- Algebra
- Computational modeling
- Logic functions
- Computer languages
- Clocks
language:
- iso: eng
place: 'Munich, Germany '
publication: Proceedings of the Design, Automation, and Test in Europe (DATE’01)
publication_identifier:
isbn:
- 0-7695-0993-2
publisher: IEEE
status: public
title: The Simulation Semantics of SystemC
type: conference
user_id: '5786'
year: '2001'
...