---
_id: '62066'
abstract:
- lang: eng
text: In the context of high-performance computing (HPC) for distributed workloads,
individual field-programmable gate arrays (FPGAs) need efficient ways to exchange
data, which requires network infrastructure and software abstractions. Dedicated
multi-FPGA clusters provide inter-FPGA networks for direct device to device communication.
The oneAPI high-level synthesis toolchain offers I/O pipes to allow user kernels
to interact with the networking ports of the FPGA board. In this work, we evaluate
using oneAPI I/O pipes for direct FPGA-to-FPGA communication by scaling a SYCL
implementation of a Jacobi solver on up to 25 FPGAs in the Noctua 2 cluster. We
see good results in weak and strong scaling experiments.
author:
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Alt C, Plessl C, Kenter T. Evaluating oneAPI I/O Pipes in a Case Study of
Scaling a SYCL Jacobi Solver to multiple FPGAs. In: Proceedings of the 13th
International Workshop on OpenCL and SYCL. IWOCL ’25. Association for Computing
Machinery; 2025. doi:10.1145/3731125.3731131'
apa: Alt, C., Plessl, C., & Kenter, T. (2025). Evaluating oneAPI I/O Pipes in
a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs. Proceedings
of the 13th International Workshop on OpenCL and SYCL. https://doi.org/10.1145/3731125.3731131
bibtex: '@inproceedings{Alt_Plessl_Kenter_2025, place={New York, NY, USA}, series={IWOCL
’25}, title={Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi
Solver to multiple FPGAs}, DOI={10.1145/3731125.3731131},
booktitle={Proceedings of the 13th International Workshop on OpenCL and SYCL},
publisher={Association for Computing Machinery}, author={Alt, Christoph and Plessl,
Christian and Kenter, Tobias}, year={2025}, collection={IWOCL ’25} }'
chicago: 'Alt, Christoph, Christian Plessl, and Tobias Kenter. “Evaluating OneAPI
I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to Multiple FPGAs.”
In Proceedings of the 13th International Workshop on OpenCL and SYCL. IWOCL
’25. New York, NY, USA: Association for Computing Machinery, 2025. https://doi.org/10.1145/3731125.3731131.'
ieee: 'C. Alt, C. Plessl, and T. Kenter, “Evaluating oneAPI I/O Pipes in a Case
Study of Scaling a SYCL Jacobi Solver to multiple FPGAs,” 2025, doi: 10.1145/3731125.3731131.'
mla: Alt, Christoph, et al. “Evaluating OneAPI I/O Pipes in a Case Study of Scaling
a SYCL Jacobi Solver to Multiple FPGAs.” Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, 2025, doi:10.1145/3731125.3731131.
short: 'C. Alt, C. Plessl, T. Kenter, in: Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, New York, NY,
USA, 2025.'
date_created: 2025-11-04T09:45:23Z
date_updated: 2025-11-04T09:47:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3731125.3731131
keyword:
- Multi-FPGA
- High-level Synthesis
- oneAPI
- FPGA
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 13th International Workshop on OpenCL and SYCL
publication_identifier:
isbn:
- '9798400713606'
publisher: Association for Computing Machinery
quality_controlled: '1'
series_title: IWOCL ’25
status: public
title: Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver
to multiple FPGAs
type: conference
user_id: '3145'
year: '2025'
...
---
_id: '21632'
abstract:
- lang: eng
text: FPGAs have found increasing adoption in data center applications since a new
generation of high-level tools have become available which noticeably reduce development
time for FPGA accelerators and still provide high-quality results. There is, however,
no high-level benchmark suite available, which specifically enables a comparison
of FPGA architectures, programming tools, and libraries for HPC applications.
To fill this gap, we have developed an OpenCL-based open-source implementation
of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve
to analyze the current capabilities of FPGA devices, cards, and development tool
flows, track progress over time, and point out specific difficulties for FPGA
acceleration in the HPC domain. Additionally, the benchmark documents proven performance
optimization patterns. We will continue optimizing and porting the benchmark for
new generations of FPGAs and design tools and encourage active participation to
create a valuable tool for the community. To fill this gap, we have developed
an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx
and Intel FPGAs. This benchmark can serve to analyze the current capabilities
of FPGA devices, cards, and development tool flows, track progress over time,
and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally,
the benchmark documents proven performance optimization patterns. We will continue
optimizing and porting the benchmark for new generations of FPGAs and design tools
and encourage active participation to create a valuable tool for the community.
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with
a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark
Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance
Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007'
apa: Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous
High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007
bibtex: '@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007},
booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and
Plessl, Christian}, year={2020} }'
chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous
High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.
ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance
with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge
Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.'
mla: Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized
OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.”
2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable
Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.
short: 'M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop
on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.'
date_created: 2021-04-16T10:17:22Z
date_updated: 2023-09-26T11:42:53Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/h2rc51942.2020.00007
keyword:
- FPGA
- OpenCL
- High Level Synthesis
- HPC benchmarking
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/9306963
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2020 IEEE/ACM International Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)
publication_identifier:
isbn:
- '9781665415927'
publication_status: published
quality_controlled: '1'
related_material:
link:
- description: Official repository of the benchmark suite on GitHub
relation: supplementary_material
url: https://github.com/pc2/HPCC_FPGA
status: public
title: Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation
of Selected Benchmarks of the HPCChallenge Benchmark Suite
type: conference
user_id: '15278'
year: '2020'
...
---
_id: '10598'
abstract:
- lang: eng
text: "Approximate computing has become a very popular design\r\nstrategy that exploits
error resilient computations to achieve higher\r\nperformance and energy efficiency.
Automated synthesis of approximate\r\ncircuits is performed via functional approximation,
in which various\r\nparts of the target circuit are extensively examined with
a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy
and computational budget (i.e., power). However, as the number\r\nof possible
approximate transformations increases, traditional search\r\ntechniques suffer
from a combinatorial explosion due to the large\r\nbranching factor. In this work,
we present a comprehensive framework\r\nfor automated synthesis of approximate
circuits from either structural\r\nor behavioral descriptions. We adapt the Monte
Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the
large design\r\nspace exploration, which enables a broader range of potential
possible\r\napproximations through lightweight random simulations. The proposed\r\nframework
is able to recognize the design Pareto set even with low\r\ncomputational budgets.
Experimental results highlight the capabilities of\r\nthe proposed synthesis framework
by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined
quality constraints."
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for
Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026'
apa: Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based
Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based
Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026},
booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner,
Marco}, year={2018}, pages={219–224} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An
MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC), 219–24,
2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework
for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.
mla: Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate
Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.'
date_created: 2019-07-10T09:21:38Z
date_updated: 2022-01-06T06:50:46Z
department:
- _id: '78'
doi: 10.1109/VLSI-SoC.2018.8645026
keyword:
- Approximate computing
- High-level synthesis
- Accuracy
- Monte-Carlo tree search
- Circuit simulation
language:
- iso: eng
page: 219-224
publication: 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)
status: public
title: An MCTS-based Framework for Synthesis of Approximate Circuits
type: conference
user_id: '64665'
year: '2018'
...