@inproceedings{10674,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}},
  keywords     = {{Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}},
  pages        = {{1--4}},
  title        = {{{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}},
  doi          = {{10.1109/FPL.2014.6927437}},
  year         = {{2014}},
}

@inproceedings{37046,
  abstract     = {{In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, we combine the native speed of an abstract real-time operating system (RTOS) model in SystemC with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU. In order to support stepwise RTOS software refinement from system level to the target software, each task can be separately migrated between the native execution and the ISS. By adapting the dynamic binary translation approach to an efficient but yet very accurate synchronization scheme the overhead of QEMU user mode execution is only factor two compared to native SystemC. Furthermore, the simulation speed increases almost linearly according to the utilization of the task set abstracted by the native execution. Hereby, the simulation time can be considerably reduced by cosimulating just a subset of tasks on QEMU.}},
  author       = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang}},
  editor       = {{Kleinjohann, L. and Kleinjohann, B.}},
  isbn         = {{978-3-642-15233-7}},
  keywords     = {{Application Programming Interface     User Mode     Kernel Space     System Level Design     Mixed Level}},
  publisher    = {{Springer Verlag}},
  title        = {{{A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement}}},
  doi          = {{10.1007/978-3-642-15234-4_15}},
  year         = {{2010}},
}

@inproceedings{39382,
  abstract     = {{We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, wait for, par, and try statements as they are introduced in SpecC. We present our definition in form of distributed abstract state machine (ASM) rules strictly following the lines of the SpecC Language Reference Manual. We mainly see our formal semantics in three application areas. First, it is a concise, unambiguous description for documentation and standardization. Second, it applies as a high-level, pseudo code-oriented specification for the implementation of a SpecC simulator. Finally, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets.}},
  author       = {{Müller, Wolfgang and Dömer, Rainer and Gerstlauer, Andreas}},
  booktitle    = {{Proceedings of the ISSS02}},
  isbn         = {{1-58113-576-9}},
  keywords     = {{Standardization, Kernel, Permission, Formal verification, Logic functions, Documentation, Reasoning about programs, Specification languages, Formal specifications, Software systems}},
  title        = {{{The Formal Execution Semantics of SpecC}}},
  doi          = {{10.1145/581199.581234 }},
  year         = {{2002}},
}

@inproceedings{39421,
  abstract     = {{We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.}},
  author       = {{Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W. and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}},
  booktitle    = {{Proceedings of the Design, Automation, and Test in Europe (DATE’01)}},
  isbn         = {{0-7695-0993-2}},
  keywords     = {{Yarn, Formal verification, Kernel, Hardware design languages, Electronic design automation and methodology, Algebra, Computational modeling, Logic functions, Computer languages, Clocks}},
  publisher    = {{IEEE}},
  title        = {{{The Simulation Semantics of SystemC}}},
  doi          = {{10.1109/DATE.2001.915002}},
  year         = {{2001}},
}

@inbook{34448,
  abstract     = {{We present a rigorous but transparent semantic definition for VHDL corresponding to the IEEE VHDL’ 93 standard [68, 9, 84]. Our definition covers the full behavior of signal and variable assignments as well as the behavior of the various wait statements including delta, time, and postponed cycles. We consider explicitly declared signals, ports, local variables, and shared variables. Our specification defines an abstract VHDL ’ 93 interpreter in the form of transition rules for an evolving algebra machine (EA-Machine) [60]. It faithfully reflects and supports the view of simulation given in the IEEE VHDL ’ 93 standard language reference manual. The definition can be understood without any prior formal training. We illustrate our definition by running the example VHDL program set out in the Introduction to this volume.}},
  author       = {{Börger, Egon and Glässer, Uwe and Müller, Wolfgang}},
  booktitle    = {{Semantics of VHDL}},
  editor       = {{Delgado Kloos, C. and Breuer, Peter T.}},
  isbn         = {{978-1-4615-2237-9}},
  keywords     = {{Transition Rule     Formal Verification     Variable Assignment     Kernel Process     Simulation Cycle}},
  pages        = {{107 -- 139}},
  publisher    = {{Kluwer Academic Publishers}},
  title        = {{{A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines}}},
  doi          = {{10.1007/978-1-4615-2237-9_5}},
  year         = {{1995}},
}