@inproceedings{10676,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2017 International Conference on Field Programmable Technology (ICFPT)}},
  keywords     = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}},
  pages        = {{215--218}},
  title        = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}},
  doi          = {{10.1109/FPT.2017.8280144}},
  year         = {{2017}},
}

@inproceedings{10674,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}},
  keywords     = {{Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}},
  pages        = {{1--4}},
  title        = {{{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}},
  doi          = {{10.1109/FPL.2014.6927437}},
  year         = {{2014}},
}

@inproceedings{10677,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}},
  keywords     = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}},
  pages        = {{31--37}},
  title        = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}},
  doi          = {{10.1109/ICES.2014.7008719}},
  year         = {{2014}},
}