--- _id: '10676' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144' apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144' bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={10.1109/FPT.2017.8280144}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }' chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In 2017 International Conference on Field Programmable Technology (ICFPT), 215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.' ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.' mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.' short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.' date_created: 2019-07-10T11:22:59Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/FPT.2017.8280144 keyword: - Linux - cache storage - microprocessor chips - multiprocessing systems - LEON3-Linux based multicore processor - MiBench suite - block sizes - cache adaptation - evolvable caches - memory-to-cache-index mapping function - processor caches - reconfigurable cache mapping optimization - reconfigurable hardware technology - replacement strategies - standard Linux OS - time a complete hardware implementation - Hardware - Indexes - Linux - Measurement - Multicore processing - Optimization - Training language: - iso: eng page: 215-218 publication: 2017 International Conference on Field Programmable Technology (ICFPT) status: public title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor' type: conference user_id: '398' year: '2017' ... --- _id: '10674' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437' apa: Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437 bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }' chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437. ieee: N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4. mla: Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437. short: 'N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.' date_created: 2019-07-10T11:18:01Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/FPL.2014.6927437 keyword: - Linux - hardware-software codesign - multiprocessing systems - parallel processing - LEON3 multicore platform - Linux kernel - PMU - hardware counters - hardware-software infrastructure - high performance embedded computing - perf_event - performance monitoring unit - Computer architecture - Hardware - Monitoring - Phasor measurement units - Radiation detectors - Registers - Software language: - iso: eng page: 1-4 project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) status: public title: A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms type: conference user_id: '3118' year: '2014' ... --- _id: '10677' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719' apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719' bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }' chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.' ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.' mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37, doi:10.1109/ICES.2014.7008719.' short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.' date_created: 2019-07-10T11:23:00Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/ICES.2014.7008719 keyword: - Linux - cache storage - embedded systems - granular computing - multiprocessing systems - reconfigurable architectures - Leon3 SPARe processor - custom logic events - evolvable-self-adaptable processor cache - fine granular profiling - integer unit events - measurement infrastructure - microarchitectural events - multicore embedded system - perf_event standard Linux performance measurement interface - processor properties - run-time reconfigurable memory-to-cache address mapping engine - run-time reconfigurable multicore infrastructure - split-level caching - Field programmable gate arrays - Frequency locked loops - Irrigation - Phasor measurement units - Registers - Weaving language: - iso: eng page: 31-37 publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) status: public title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure' type: conference user_id: '3118' year: '2014' ...