@inproceedings{39382,
  abstract     = {{We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, wait for, par, and try statements as they are introduced in SpecC. We present our definition in form of distributed abstract state machine (ASM) rules strictly following the lines of the SpecC Language Reference Manual. We mainly see our formal semantics in three application areas. First, it is a concise, unambiguous description for documentation and standardization. Second, it applies as a high-level, pseudo code-oriented specification for the implementation of a SpecC simulator. Finally, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets.}},
  author       = {{Müller, Wolfgang and Dömer, Rainer and Gerstlauer, Andreas}},
  booktitle    = {{Proceedings of the ISSS02}},
  isbn         = {{1-58113-576-9}},
  keywords     = {{Standardization, Kernel, Permission, Formal verification, Logic functions, Documentation, Reasoning about programs, Specification languages, Formal specifications, Software systems}},
  title        = {{{The Formal Execution Semantics of SpecC}}},
  doi          = {{10.1145/581199.581234 }},
  year         = {{2002}},
}

@inproceedings{39421,
  abstract     = {{We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.}},
  author       = {{Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W. and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}},
  booktitle    = {{Proceedings of the Design, Automation, and Test in Europe (DATE’01)}},
  isbn         = {{0-7695-0993-2}},
  keywords     = {{Yarn, Formal verification, Kernel, Hardware design languages, Electronic design automation and methodology, Algebra, Computational modeling, Logic functions, Computer languages, Clocks}},
  publisher    = {{IEEE}},
  title        = {{{The Simulation Semantics of SystemC}}},
  doi          = {{10.1109/DATE.2001.915002}},
  year         = {{2001}},
}