@inproceedings{36994,
  abstract     = {{This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP.}},
  author       = {{Xie, Tao  and Müller, Wolfgang and Letombe, Florian}},
  booktitle    = {{Proceedings of SOCC2012}},
  keywords     = {{Analytical models, Hardware design languages, Microprocessors, Cost function, Data models, Search problems, IP networks}},
  publisher    = {{IEEE}},
  title        = {{{Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}}},
  doi          = {{10.1109/SOCC.2012.6398362}},
  year         = {{2012}},
}