@inproceedings{63758,
  abstract     = {{Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. This paper presents the migration of TETRISC to the Rocket Chip SoC, which is freely scalable to the number of processors through parametrizable Chisel models. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis for the rapid prototyping of resilient, scalable architectures that are online configurable through software for different multicore and lock-step modes.}},
  author       = {{Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}},
  booktitle    = {{38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}},
  keywords     = {{RISC-V, Multicore, Fault Tolerant, TETRISC, Chisel, Chipyard}},
  location     = {{Potsdam}},
  title        = {{{Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations}}},
  year         = {{2026}},
}

@inproceedings{10676,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2017 International Conference on Field Programmable Technology (ICFPT)}},
  keywords     = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}},
  pages        = {{215--218}},
  title        = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}},
  doi          = {{10.1109/FPT.2017.8280144}},
  year         = {{2017}},
}

@inproceedings{10780,
  author       = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}},
  booktitle    = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}},
  keywords     = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}},
  pages        = {{1--8}},
  title        = {{{Computational self-awareness as design approach for visual sensor nodes}}},
  doi          = {{10.1109/ReCoSoC.2017.8016147}},
  year         = {{2017}},
}

@inproceedings{10673,
  author       = {{Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}},
  keywords     = {{cache storage, field programmable gate arrays, multiprocessing systems, parallel architectures, reconfigurable architectures, FPGA, dynamic reconfiguration, evolvable cache mapping, many-core architecture, memory-to-cache address mapping function, microarchitectural optimization, multicore architecture, nature-inspired optimization, parallelization degrees, processor, reconfigurable cache mapping, reconfigurable computing, Field programmable gate arrays, Software, Tuning}},
  pages        = {{1--7}},
  title        = {{{Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}}},
  doi          = {{10.1109/AHS.2015.7231178}},
  year         = {{2015}},
}

@inproceedings{10674,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}},
  keywords     = {{Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}},
  pages        = {{1--4}},
  title        = {{{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}},
  doi          = {{10.1109/FPL.2014.6927437}},
  year         = {{2014}},
}

@inproceedings{10677,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}},
  keywords     = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}},
  pages        = {{31--37}},
  title        = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}},
  doi          = {{10.1109/ICES.2014.7008719}},
  year         = {{2014}},
}