[{"year":"2026","title":"Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations","status":"public","author":[{"full_name":"Hannemann, Kai Arne","last_name":"Hannemann","first_name":"Kai Arne","id":"63972"},{"full_name":"Luchterhandt, Lars","last_name":"Luchterhandt","first_name":"Lars","id":"74648"},{"full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang","id":"16243"},{"last_name":"Ulbricht","first_name":"Markus","full_name":"Ulbricht, Markus"},{"full_name":"Lu, Li","first_name":"Li","last_name":"Lu"}],"conference":{"location":"Potsdam","start_date":"2026-02-22","name":"38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen","end_date":"2026-02-24"},"date_updated":"2026-07-16T11:08:27Z","has_accepted_license":"1","language":[{"iso":"eng"}],"_id":"63758","user_id":"63972","publication":"38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen","citation":{"chicago":"Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” In <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>. Potsdam, 2026.","short":"K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, in: 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen, Potsdam, 2026.","apa":"Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., &#38; Lu, L. (2026). Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations. <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>. 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Potsdam.","ieee":"K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Potsdam, 2026.","ama":"Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L. Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations. In: <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>. ; 2026.","bibtex":"@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_2026, place={Potsdam}, title={Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations}, booktitle={38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}, year={2026} }","mla":"Hannemann, Kai Arne, et al. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>, 2026."},"abstract":[{"text":"Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. This paper presents the migration of TETRISC to the Rocket Chip SoC, which is freely scalable to the number of processors through parametrizable Chisel models. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis for the rapid prototyping of resilient, scalable architectures that are online configurable through software for different multicore and lock-step modes.","lang":"eng"}],"date_created":"2026-01-27T13:14:51Z","place":"Potsdam","type":"conference","keyword":["RISC-V","Multicore","Fault Tolerant","TETRISC","Chisel","Chipyard"],"department":[{"_id":"58"}]},{"author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"status":"public","title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","year":"2017","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"_id":"10676","page":"215-218","user_id":"398","doi":"10.1109/FPT.2017.8280144","citation":{"ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–218.","mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–18, doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i> (pp. 215–218). <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 215–18, 2017. <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>.","ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>. ; 2017:215-218. doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218."},"publication":"2017 International Conference on Field Programmable Technology (ICFPT)","date_created":"2019-07-10T11:22:59Z","department":[{"_id":"78"}],"keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"type":"conference"},{"user_id":"3118","doi":"10.1109/ReCoSoC.2017.8016147","language":[{"iso":"eng"}],"_id":"10780","page":"1-8","date_updated":"2022-01-06T06:50:50Z","author":[{"full_name":"Guettatfi, Zakarya","last_name":"Guettatfi","first_name":"Zakarya"},{"last_name":"Hübner","first_name":"Philipp","full_name":"Hübner, Philipp"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"},{"full_name":"Rinner, Bernhard","last_name":"Rinner","first_name":"Bernhard"}],"title":"Computational self-awareness as design approach for visual sensor nodes","status":"public","year":"2017","department":[{"_id":"78"}],"type":"conference","keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"date_created":"2019-07-10T12:13:15Z","citation":{"chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 1–8, 2017. <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>.","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2017:1-8. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","apa":"Guettatfi, Z., Hübner, P., Platzner, M., &#38; Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>.","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8."},"publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)"},{"date_updated":"2022-01-06T06:50:49Z","year":"2015","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","status":"public","author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"last_name":"Ahmed","first_name":"Abdullah Fathi","full_name":"Ahmed, Abdullah Fathi"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"user_id":"3118","doi":"10.1109/AHS.2015.7231178","page":"1-7","language":[{"iso":"eng"}],"_id":"10673","project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","citation":{"mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7, doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>.","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., &#38; Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i> (pp. 1–7). <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7.","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>.","short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7."},"keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T11:18:00Z"},{"status":"public","title":"A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms","year":"2014","author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"date_updated":"2022-01-06T06:50:49Z","page":"1-4","language":[{"iso":"eng"}],"_id":"10674","user_id":"3118","doi":"10.1109/FPL.2014.6927437","publication":"24th Intl. Conf. on Field Programmable Logic and Applications (FPL)","citation":{"bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }","ama":"Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>. ; 2014:1-4. doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4, doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 1–4, 2014. <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i> (pp. 1–4). <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>"},"project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"date_created":"2019-07-10T11:18:01Z","keyword":["Linux","hardware-software codesign","multiprocessing systems","parallel processing","LEON3 multicore platform","Linux kernel","PMU","hardware counters","hardware-software infrastructure","high performance embedded computing","perf_event","performance monitoring unit","Computer architecture","Hardware","Monitoring","Phasor measurement units","Radiation detectors","Registers","Software"],"type":"conference","department":[{"_id":"78"}]},{"author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","year":"2014","status":"public","date_updated":"2022-01-06T06:50:49Z","_id":"10677","language":[{"iso":"eng"}],"page":"31-37","doi":"10.1109/ICES.2014.7008719","user_id":"3118","citation":{"bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>. ; 2014:31-37. doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37.","mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37, doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i> (pp. 31–37). <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>"},"publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","date_created":"2019-07-10T11:23:00Z","department":[{"_id":"78"}],"type":"conference","keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"]}]