---
_id: '63758'
abstract:
- lang: eng
text: Resilient systems require monitoring and prediction of environmental and intrinsic
conditions and the ability to adapt to changing circumstances to optimize the
trade-off between performance, power consumption, and fault tolerance. TETRISC
was introduced as a resilient multicore RISC-V processor system based on the PULPissimo
platform. This paper presents the migration of TETRISC to the Rocket Chip SoC,
which is freely scalable to the number of processors through parametrizable Chisel
models. As such, we discuss and evaluate the main advantages and obstacles that
come with the Chipyard framework for RTL simulation and FPGA synthesis for the
rapid prototyping of resilient, scalable architectures that are online configurable
through software for different multicore and lock-step modes.
author:
- first_name: Kai Arne
full_name: Hannemann, Kai Arne
id: '63972'
last_name: Hannemann
- first_name: Lars
full_name: Luchterhandt, Lars
last_name: Luchterhandt
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Markus
full_name: Ulbricht, Markus
last_name: Ulbricht
- first_name: Li
full_name: Lu, Li
last_name: Lu
citation:
ama: 'Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L. Redesigning the
TETRISC Architecture for Scalable Rocket Chip Implementations. In: 38. ITG
/ GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen.
; 2026.'
apa: Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., & Lu, L.
(2026). Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.
38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen
Und Systemen. 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen, Potsdam.
bibtex: '@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_2026, place={Potsdam},
title={Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations},
booktitle={38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von
Schaltungen und Systemen}, author={Hannemann, Kai Arne and Luchterhandt, Lars
and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}, year={2026} }'
chicago: Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht,
and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.”
In 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen
Und Systemen. Potsdam, 2026.
ieee: K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning
the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented
at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen, Potsdam, 2026.
mla: Hannemann, Kai Arne, et al. “Redesigning the TETRISC Architecture for Scalable
Rocket Chip Implementations.” 38. ITG / GMM / GI - Workshop Testmethoden Und
Zuverlässigkeit von Schaltungen Und Systemen, 2026.
short: 'K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, in: 38.
ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und
Systemen, Potsdam, 2026.'
conference:
end_date: 2026-02-24
location: Potsdam
name: 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen
start_date: 2026-02-22
date_created: 2026-01-27T13:14:51Z
date_updated: 2026-05-08T09:08:14Z
department:
- _id: '58'
has_accepted_license: '1'
keyword:
- RISC-V
- Multicore
- Fault Tolerant
- TETRISC
- Chisel
- Chipyard
language:
- iso: eng
place: Potsdam
publication: 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen
status: public
title: Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations
type: conference
user_id: '63972'
year: '2026'
...
---
_id: '10676'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International
Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
In 2017 International Conference on Field Programmable Technology (ICFPT)
(pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor},
DOI={10.1109/FPT.2017.8280144},
booktitle={2017 International Conference on Field Programmable Technology (ICFPT)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218}
}'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization
of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”
In 2017 International Conference on Field Programmable Technology (ICFPT),
215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International
Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.'
mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings
for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference
on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field
Programmable Technology (ICFPT), 2017, pp. 215–218.'
date_created: 2019-07-10T11:22:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPT.2017.8280144
keyword:
- Linux
- cache storage
- microprocessor chips
- multiprocessing systems
- LEON3-Linux based multicore processor
- MiBench suite
- block sizes
- cache adaptation
- evolvable caches
- memory-to-cache-index mapping function
- processor caches
- reconfigurable cache mapping optimization
- reconfigurable hardware technology
- replacement strategies
- standard Linux OS
- time a complete hardware implementation
- Hardware
- Indexes
- Linux
- Measurement
- Multicore processing
- Optimization
- Training
language:
- iso: eng
page: 215-218
publication: 2017 International Conference on Field Programmable Technology (ICFPT)
status: public
title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based
multi-core processor'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '10780'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Philipp
full_name: Hübner, Philipp
last_name: Hübner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: 'Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness
as design approach for visual sensor nodes. In: 12th International Symposium
on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8.
doi:10.1109/ReCoSoC.2017.8016147'
apa: Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational
self-awareness as design approach for visual sensor nodes. In 12th International
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
(pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147
bibtex: '@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational
self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147},
booktitle={12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and
Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }'
chicago: Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner.
“Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In
12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip
(ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.
ieee: Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness
as design approach for visual sensor nodes,” in 12th International Symposium
on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp.
1–8.
mla: Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach
for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric
Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.
short: 'Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International
Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017,
pp. 1–8.'
date_created: 2019-07-10T12:13:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ReCoSoC.2017.8016147
keyword:
- embedded systems
- image sensors
- power aware computing
- wireless sensor networks
- Zynq-based VSN node prototype
- computational self-awareness
- design approach
- platform levels
- power consumption
- visual sensor networks
- visual sensor nodes
- Cameras
- Hardware
- Middleware
- Multicore processing
- Operating systems
- Runtime
- Reconfigurable platforms
- distributed embedded systems
- performance-resource trade-off
- self-awareness
- visual sensor nodes
language:
- iso: eng
page: 1-8
publication: 12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)
status: public
title: Computational self-awareness as design approach for visual sensor nodes
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10673'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Abdullah Fathi
full_name: Ahmed, Abdullah Fathi
last_name: Ahmed
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf.
Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178'
apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings. In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178
bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178},
booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
pages={1–7} }'
chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.
ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA
Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.
mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems
(AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
mappings
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10674'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance
monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437'
apa: Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure
for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437},
booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4}
}'
chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure
for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf.
on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437.
ieee: N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for
performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on
Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.
mla: Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring
on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic
and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable
Logic and Applications (FPL), 2014, pp. 1–4.'
date_created: 2019-07-10T11:18:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPL.2014.6927437
keyword:
- Linux
- hardware-software codesign
- multiprocessing systems
- parallel processing
- LEON3 multicore platform
- Linux kernel
- PMU
- hardware counters
- hardware-software infrastructure
- high performance embedded computing
- perf_event
- performance monitoring unit
- Computer architecture
- Hardware
- Monitoring
- Phasor measurement units
- Radiation detectors
- Registers
- Software
language:
- iso: eng
page: 1-4
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL)
status: public
title: A hardware/software infrastructure for performance monitoring on LEON3 multicore
platforms
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10677'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems
(ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches:
A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf.
on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719},
booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl.
Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014,
pp. 31–37, doi:10.1109/ICES.2014.7008719.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...