[{"author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"publication":"2017 International Conference on Field Programmable Technology (ICFPT)","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:22:59Z","user_id":"398","title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","language":[{"iso":"eng"}],"type":"conference","citation":{"bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={10.1109/FPT.2017.8280144}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }","mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144","ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In 2017 International Conference on Field Programmable Technology (ICFPT), 215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218."},"year":"2017","page":"215-218","date_updated":"2022-01-06T06:50:49Z","_id":"10676","doi":"10.1109/FPT.2017.8280144"},{"title":"Computational self-awareness as design approach for visual sensor nodes","user_id":"3118","keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"department":[{"_id":"78"}],"publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","author":[{"last_name":"Guettatfi","full_name":"Guettatfi, Zakarya","first_name":"Zakarya"},{"last_name":"Hübner","first_name":"Philipp","full_name":"Hübner, Philipp"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","full_name":"Rinner, Bernhard","first_name":"Bernhard"}],"date_created":"2019-07-10T12:13:15Z","status":"public","_id":"10780","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/ReCoSoC.2017.8016147","page":"1-8","citation":{"ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. 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