[{"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","date_created":"2021-04-16T10:17:22Z","year":"2020","quality_controlled":"1","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community."}],"publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"doi":"10.1109/h2rc51942.2020.00007","date_updated":"2023-09-26T11:42:53Z","author":[{"first_name":"Marius","last_name":"Meyer","full_name":"Meyer, Marius","id":"40778"},{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"citation":{"apa":"Meyer, M., Kenter, T., &#38; Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>. <a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">https://doi.org/10.1109/h2rc51942.2020.00007</a>","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={<a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2020, doi:<a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>.","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: <a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>.","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2020. <a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">https://doi.org/10.1109/h2rc51942.2020.00007</a>.","ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: <i>2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>. ; 2020. doi:<a href=\"https://doi.org/10.1109/h2rc51942.2020.00007\">10.1109/h2rc51942.2020.00007</a>"},"publication_status":"published","publication_identifier":{"isbn":["9781665415927"]},"related_material":{"link":[{"url":"https://github.com/pc2/HPCC_FPGA","relation":"supplementary_material","description":"Official repository of the benchmark suite on GitHub"}]},"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"_id":"21632","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"status":"public","type":"conference"},{"language":[{"iso":"eng"}],"keyword":["FFT: FPGA","CP2K","OpenCL"],"ddc":["000"],"file":[{"date_updated":"2020-06-15T11:29:38Z","creator":"arjunr","date_created":"2020-06-15T11:29:38Z","file_size":1297585,"file_name":"masterthesis.pdf","access_level":"closed","file_id":"17093","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"lang":"eng","text":"Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs."}],"title":"Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA","date_created":"2018-11-07T16:08:32Z","publisher":"Universität Paderborn","year":"2018","file_date_updated":"2020-06-15T11:29:38Z","department":[{"_id":"27"},{"_id":"518"}],"user_id":"49171","_id":"5417","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"status":"public","type":"mastersthesis","main_file_link":[{"open_access":"1"}],"supervisor":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"author":[{"first_name":"Arjun","last_name":"Ramaswami","orcid":"https://orcid.org/0000-0002-0909-1178","id":"49171","full_name":"Ramaswami, Arjun"}],"oa":"1","date_updated":"2022-01-12T16:32:23Z","citation":{"apa":"Ramaswami, A. (2018). <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn.","mla":"Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","bibtex":"@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn}, author={Ramaswami, Arjun}, year={2018} }","short":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA, Universität Paderborn, 2018.","chicago":"Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","ieee":"A. Ramaswami, <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","ama":"Ramaswami A. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn; 2018."},"has_accepted_license":"1"}]