[{"type":"conference","publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","status":"public","_id":"10780","user_id":"3118","department":[{"_id":"78"}],"keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"language":[{"iso":"eng"}],"year":"2017","citation":{"ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2017:1-8. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8.","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 1–8, 2017. <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>.","apa":"Guettatfi, Z., Hübner, P., Platzner, M., &#38; Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>","bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>."},"page":"1-8","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Guettatfi","full_name":"Guettatfi, Zakarya","first_name":"Zakarya"},{"first_name":"Philipp","last_name":"Hübner","full_name":"Hübner, Philipp"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"last_name":"Rinner","full_name":"Rinner, Bernhard","first_name":"Bernhard"}],"date_created":"2019-07-10T12:13:15Z","title":"Computational self-awareness as design approach for visual sensor nodes","doi":"10.1109/ReCoSoC.2017.8016147"},{"citation":{"apa":"Guettatfi, Z., Kermia, O., &#38; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>","short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, Imperial College, 2015, doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>.","chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College, 2015. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>.","ieee":"Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2015.","ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College; 2015. doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>"},"year":"2015","publication_identifier":{"issn":["1946-147X"]},"doi":"10.1109/FPL.2015.7293994","title":"Over effective hard real-time hardware tasks scheduling and allocation","date_created":"2019-07-10T12:11:36Z","author":[{"full_name":"Guettatfi, Zakarya","last_name":"Guettatfi","first_name":"Zakarya"},{"first_name":"Omar","last_name":"Kermia","full_name":"Kermia, Omar"},{"full_name":"Khouas, Abdelhakim","last_name":"Khouas","first_name":"Abdelhakim"}],"date_updated":"2022-01-06T06:50:50Z","publisher":"Imperial College","status":"public","type":"conference","publication":"25th International Conference on Field Programmable Logic and Applications (FPL)","language":[{"iso":"eng"}],"extern":"1","keyword":["embedded systems","field programmable gate arrays","operating systems (computers)","scheduling","μC/OS-II","FPGAs","OS foundation","SafeRTOS","Xenomai","chip utilization ration","complex time constraints","embedded systems","hard real-time hardware task allocation","hard real-time hardware task scheduling","hardware-software real-time operating systems","partially reconfigurable field-programmable gate arrays","resource constraints","safety-critical RTOS","Field programmable gate arrays","Hardware","Job shop scheduling","Real-time systems","Shape","Software"],"user_id":"398","department":[{"_id":"78"}],"_id":"10779"},{"language":[{"iso":"eng"}],"keyword":["Unified modeling language","Field programmable gate arrays","Bridges","Helium","Real time systems","Operating systems","Documentation","Application software","XML","Space exploration"],"department":[{"_id":"672"}],"user_id":"5786","_id":"37007","status":"public","abstract":[{"text":"UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.","lang":"eng"}],"publication":"Proceedings of DATE’10","type":"conference","doi":"10.1109/DATE.2010.5456990","conference":{"location":"Dresden","name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"title":"Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems","date_created":"2023-01-17T09:12:35Z","author":[{"full_name":"Mischkalla, Fabian","last_name":"Mischkalla","first_name":"Fabian"},{"first_name":"Da","last_name":"He","full_name":"He, Da"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"date_updated":"2023-01-17T09:12:44Z","publisher":"IEEE","citation":{"ama":"Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>","chicago":"Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>.","ieee":"F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>.","apa":"Mischkalla, F., He, D., &#38; Müller, W. (2010). Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>","mla":"Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>.","bibtex":"@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian and He, Da and Müller, Wolfgang}, year={2010} }","short":"F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010."},"year":"2010","place":"Dresden","publication_identifier":{"eisbn":["978-3-9810801-6-2"]}},{"date_created":"2023-01-17T09:15:10Z","author":[{"last_name":"Oliveira","full_name":"Oliveira, Marcio F. S.","first_name":"Marcio F. S."},{"first_name":"Henning","last_name":"Zabel","full_name":"Zabel, Henning"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"date_updated":"2023-01-17T09:15:18Z","publisher":"IEEE","conference":{"location":"Dresden","name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"doi":"10.1109/DATE.2010.5457130","title":"Assertion-Based Verification of RTOS Properties","citation":{"ama":"Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>","ieee":"M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification of RTOS Properties,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>.","chicago":"Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based Verification of RTOS Properties.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">https://doi.org/10.1109/DATE.2010.5457130</a>.","short":"M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","mla":"Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>.","bibtex":"@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based Verification of RTOS Properties}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }","apa":"Oliveira, M. F. S., Zabel, H., &#38; Müller, W. (2010). Assertion-Based Verification of RTOS Properties. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">https://doi.org/10.1109/DATE.2010.5457130</a>"},"place":"Dresden","year":"2010","department":[{"_id":"672"}],"user_id":"5786","_id":"37009","language":[{"iso":"eng"}],"keyword":["Operating systems","Real time systems","Timing","Hardware","Analytical models","Embedded software","Software systems","Processor scheduling","Software performance","Performance analysis"],"publication":"Proceedings of DATE’10","type":"conference","status":"public","abstract":[{"text":"Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.","lang":"eng"}]},{"publication":"Proceedings of DATE’10","type":"conference","abstract":[{"text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.","lang":"eng"}],"status":"public","_id":"37040","department":[{"_id":"672"}],"user_id":"5786","keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"language":[{"iso":"eng"}],"publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"place":"Dresden","year":"2010","citation":{"chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>.","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>","mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }"},"publisher":"IEEE","date_updated":"2023-01-17T10:47:37Z","author":[{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"first_name":"Giuseppe","full_name":"Di Guglielmo, Giuseppe","last_name":"Di Guglielmo"},{"last_name":"Fummi","full_name":"Fummi, Franco","first_name":"Franco"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"},{"last_name":"Pravadelli","full_name":"Pravadelli, Graziano","first_name":"Graziano"},{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"}],"date_created":"2023-01-17T10:47:29Z","title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","doi":"10.1109/DATE.2010.5456965","conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"}},{"date_updated":"2023-01-17T11:28:30Z","publisher":"IEEE","author":[{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"Marcio F.","full_name":"da S. Oliveira, Marcio F.","last_name":"da S. Oliveira"},{"full_name":"Zabel, Henning","last_name":"Zabel","first_name":"Henning"},{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"}],"date_created":"2023-01-17T11:28:26Z","title":"Verification of Real-Time Properties for Hardware-Dependant Software","conference":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT)","location":"Anaheim, FL, USA"},"publication_identifier":{"eisbn":["978-1-4244-7806-4"]},"year":"2010","citation":{"apa":"Müller, W., da S. Oliveira, M. F., Zabel, H., &#38; Becker, M. (2010). Verification of Real-Time Properties for Hardware-Dependant Software. <i>Proceedings of HLDVT2010</i>. IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA.","bibtex":"@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }","mla":"Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant Software.” <i>Proceedings of HLDVT2010</i>, IEEE, 2010.","short":"W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of HLDVT2010, IEEE, 2010.","ama":"Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time Properties for Hardware-Dependant Software. In: <i>Proceedings of HLDVT2010</i>. IEEE; 2010.","chicago":"Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker. “Verification of Real-Time Properties for Hardware-Dependant Software.” In <i>Proceedings of HLDVT2010</i>. IEEE, 2010.","ieee":"W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010."},"_id":"37053","department":[{"_id":"672"}],"user_id":"5786","keyword":["Hardware","Microprogramming","Application software","Timing","Protocols","Virtual prototyping","Real time systems","Sampling methods","Operating systems","Emulation"],"language":[{"iso":"eng"}],"publication":"Proceedings of HLDVT2010","type":"conference","abstract":[{"lang":"eng","text":"Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models."}],"status":"public"},{"date_updated":"2025-03-12T16:39:17Z","publisher":"IEEE","date_created":"2023-01-17T10:44:46Z","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"first_name":"Giuseppe","full_name":"Di Guglielmo, Giuseppe","last_name":"Di Guglielmo"},{"full_name":"Fummi, Franco","last_name":"Fummi","first_name":"Franco"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Graziano","last_name":"Pravadelli","full_name":"Pravadelli, Graziano"},{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"}],"title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","doi":"10.1109/DATE.2010.5456965","conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"},"publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"year":"2010","place":"Dresden","citation":{"ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>.","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>","mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }"},"_id":"37039","user_id":"5786","keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"language":[{"iso":"eng"}],"publication":"Proceedings of DATE’10","type":"conference","abstract":[{"lang":"eng","text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms."}],"status":"public"},{"title":"ReconOS: Multithreaded Programming for Reconfigurable Computers","doi":"10.1145/1596532.1596540","date_updated":"2022-01-06T06:50:50Z","volume":9,"author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:41:17Z","year":"2009","intvolume":"         9","page":"8:1-8:33","citation":{"apa":"Lübbers, E., &#38; Platzner, M. (2009). ReconOS: Multithreaded Programming for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>, <i>9</i>(1), 8:1-8:33. <a href=\"https://doi.org/10.1145/1596532.1596540\">https://doi.org/10.1145/1596532.1596540</a>","short":"E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33.","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>.","bibtex":"@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming for Reconfigurable Computers}, volume={9}, DOI={<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>}, number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers, Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }","ama":"Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>. 2009;9(1):8:1-8:33. doi:<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>","ieee":"E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no. 1, pp. 8:1-8:33, 2009.","chicago":"Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i> 9, no. 1 (2009): 8:1-8:33. <a href=\"https://doi.org/10.1145/1596532.1596540\">https://doi.org/10.1145/1596532.1596540</a>."},"publication_identifier":{"issn":["1539-9087"]},"issue":"1","keyword":["Reconfigurable computing","multithreading","operating systems"],"language":[{"iso":"eng"}],"_id":"10703","department":[{"_id":"78"}],"user_id":"3118","status":"public","publication":"ACM Transactions on Embedded Computing Systems","type":"journal_article"},{"abstract":[{"text":"Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.","lang":"eng"}],"status":"public","type":"conference","publication":"Proceedings of DATE'09","keyword":["Timing","Analytical models","Clocks","Performance analysis","Scheduling","Operating systems","Delay","Real time systems","Application software","Context modeling"],"language":[{"iso":"eng"}],"_id":"37066","user_id":"5786","department":[{"_id":"672"}],"year":"2009","place":"Nice, France","citation":{"chicago":"Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise Injection in Abstract RTOS Simulation.” In <i>Proceedings of DATE’09</i>. Nice, France, 2009. <a href=\"https://doi.org/10.1109/DATE.2009.5090925\">https://doi.org/10.1109/DATE.2009.5090925</a>.","ieee":"H. Zabel and W. Müller, “Increased Accuracy through Noise Injection in Abstract RTOS Simulation,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition, 2009, doi: <a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>.","ama":"Zabel H, Müller W. Increased Accuracy through Noise Injection in Abstract RTOS Simulation. In: <i>Proceedings of DATE’09</i>. ; 2009. doi:<a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>","mla":"Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise Injection in Abstract RTOS Simulation.” <i>Proceedings of DATE’09</i>, 2009, doi:<a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>.","short":"H. Zabel, W. Müller, in: Proceedings of DATE’09, Nice, France, 2009.","bibtex":"@inproceedings{Zabel_Müller_2009, place={Nice, France}, title={Increased Accuracy through Noise Injection in Abstract RTOS Simulation}, DOI={<a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>}, booktitle={Proceedings of DATE’09}, author={Zabel, Henning and Müller, Wolfgang}, year={2009} }","apa":"Zabel, H., &#38; Müller, W. (2009). Increased Accuracy through Noise Injection in Abstract RTOS Simulation. <i>Proceedings of DATE’09</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition. <a href=\"https://doi.org/10.1109/DATE.2009.5090925\">https://doi.org/10.1109/DATE.2009.5090925</a>"},"publication_identifier":{"isbn":["978-1-4244-3781-8"]},"title":"Increased Accuracy through Noise Injection in Abstract RTOS Simulation","doi":"10.1109/DATE.2009.5090925","conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition"},"date_updated":"2023-01-17T11:51:48Z","author":[{"first_name":"Henning","full_name":"Zabel, Henning","last_name":"Zabel"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"date_created":"2023-01-17T11:51:44Z"},{"date_updated":"2023-01-24T08:18:27Z","date_created":"2023-01-24T08:18:10Z","author":[{"last_name":"Schattkowsky","full_name":"Schattkowsky, Tim","first_name":"Tim"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}],"title":"Transformation of UML State Machines for Direct Execution","doi":"10.1109/VLHCC.2005.64","publication_identifier":{"isbn":["0-7695-2443-5"]},"year":"2005","place":"Dallas, TX, USA","citation":{"short":"T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA, 2005.","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Dallas, TX, USA}, title={Transformation of UML State Machines for Direct Execution}, DOI={<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>}, booktitle={Proceedings of VL/HCC 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }","mla":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” <i>Proceedings of VL/HCC 05</i>, 2005, doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","apa":"Schattkowsky, T., &#38; Müller, W. (2005). Transformation of UML State Machines for Direct Execution. <i>Proceedings of VL/HCC 05</i>. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>","ama":"Schattkowsky T, Müller W. Transformation of UML State Machines for Direct Execution. In: <i>Proceedings of VL/HCC 05</i>. ; 2005. doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>","chicago":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” In <i>Proceedings of VL/HCC 05</i>. Dallas, TX, USA, 2005. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>.","ieee":"T. Schattkowsky and W. Müller, “Transformation of UML State Machines for Direct Execution,” 2005, doi: <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>."},"_id":"39032","department":[{"_id":"672"}],"user_id":"5786","keyword":["Unified modeling language","Software design","Virtual machining","Embedded system","Programming","Documentation","Hardware","Computer languages","Operating systems","Runtime"],"language":[{"iso":"eng"}],"publication":"Proceedings of VL/HCC 05","type":"conference","abstract":[{"text":"Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.","lang":"eng"}],"status":"public"}]