---
_id: '10780'
author:
- first_name: Zakarya
  full_name: Guettatfi, Zakarya
  last_name: Guettatfi
- first_name: Philipp
  full_name: Hübner, Philipp
  last_name: Hübner
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Bernhard
  full_name: Rinner, Bernhard
  last_name: Rinner
citation:
  ama: 'Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness
    as design approach for visual sensor nodes. In: <i>12th International Symposium
    on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2017:1-8.
    doi:<a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">10.1109/ReCoSoC.2017.8016147</a>'
  apa: Guettatfi, Z., Hübner, P., Platzner, M., &#38; Rinner, B. (2017). Computational
    self-awareness as design approach for visual sensor nodes. In <i>12th International
    Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>
    (pp. 1–8). <a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>
  bibtex: '@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational
    self-awareness as design approach for visual sensor nodes}, DOI={<a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">10.1109/ReCoSoC.2017.8016147</a>},
    booktitle={12th International Symposium on Reconfigurable Communication-centric
    Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and
    Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }'
  chicago: Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner.
    “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In
    <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip
    (ReCoSoC)</i>, 1–8, 2017. <a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>.
  ieee: Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness
    as design approach for visual sensor nodes,” in <i>12th International Symposium
    on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp.
    1–8.
  mla: Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach
    for Visual Sensor Nodes.” <i>12th International Symposium on Reconfigurable Communication-Centric
    Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8, doi:<a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">10.1109/ReCoSoC.2017.8016147</a>.
  short: 'Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International
    Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017,
    pp. 1–8.'
date_created: 2019-07-10T12:13:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ReCoSoC.2017.8016147
keyword:
- embedded systems
- image sensors
- power aware computing
- wireless sensor networks
- Zynq-based VSN node prototype
- computational self-awareness
- design approach
- platform levels
- power consumption
- visual sensor networks
- visual sensor nodes
- Cameras
- Hardware
- Middleware
- Multicore processing
- Operating systems
- Runtime
- Reconfigurable platforms
- distributed embedded systems
- performance-resource trade-off
- self-awareness
- visual sensor nodes
language:
- iso: eng
page: 1-8
publication: 12th International Symposium on Reconfigurable Communication-centric
  Systems-on-Chip (ReCoSoC)
status: public
title: Computational self-awareness as design approach for visual sensor nodes
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10779'
author:
- first_name: Zakarya
  full_name: Guettatfi, Zakarya
  last_name: Guettatfi
- first_name: Omar
  full_name: Kermia, Omar
  last_name: Kermia
- first_name: Abdelhakim
  full_name: Khouas, Abdelhakim
  last_name: Khouas
citation:
  ama: 'Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks
    scheduling and allocation. In: <i>25th International Conference on Field Programmable
    Logic and Applications (FPL)</i>. Imperial College; 2015. doi:<a href="https://doi.org/10.1109/FPL.2015.7293994">10.1109/FPL.2015.7293994</a>'
  apa: Guettatfi, Z., Kermia, O., &#38; Khouas, A. (2015). Over effective hard real-time
    hardware tasks scheduling and allocation. In <i>25th International Conference
    on Field Programmable Logic and Applications (FPL)</i>. Imperial College. <a href="https://doi.org/10.1109/FPL.2015.7293994">https://doi.org/10.1109/FPL.2015.7293994</a>
  bibtex: '@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard
    real-time hardware tasks scheduling and allocation}, DOI={<a href="https://doi.org/10.1109/FPL.2015.7293994">10.1109/FPL.2015.7293994</a>},
    booktitle={25th International Conference on Field Programmable Logic and Applications
    (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar
    and Khouas, Abdelhakim}, year={2015} }'
  chicago: Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective
    Hard Real-Time Hardware Tasks Scheduling and Allocation.” In <i>25th International
    Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College,
    2015. <a href="https://doi.org/10.1109/FPL.2015.7293994">https://doi.org/10.1109/FPL.2015.7293994</a>.
  ieee: Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware
    tasks scheduling and allocation,” in <i>25th International Conference on Field
    Programmable Logic and Applications (FPL)</i>, 2015.
  mla: Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling
    and Allocation.” <i>25th International Conference on Field Programmable Logic
    and Applications (FPL)</i>, Imperial College, 2015, doi:<a href="https://doi.org/10.1109/FPL.2015.7293994">10.1109/FPL.2015.7293994</a>.
  short: 'Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on
    Field Programmable Logic and Applications (FPL), Imperial College, 2015.'
date_created: 2019-07-10T12:11:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPL.2015.7293994
extern: '1'
keyword:
- embedded systems
- field programmable gate arrays
- operating systems (computers)
- scheduling
- μC/OS-II
- FPGAs
- OS foundation
- SafeRTOS
- Xenomai
- chip utilization ration
- complex time constraints
- embedded systems
- hard real-time hardware task allocation
- hard real-time hardware task scheduling
- hardware-software real-time operating systems
- partially reconfigurable field-programmable gate arrays
- resource constraints
- safety-critical RTOS
- Field programmable gate arrays
- Hardware
- Job shop scheduling
- Real-time systems
- Shape
- Software
language:
- iso: eng
publication: 25th International Conference on Field Programmable Logic and Applications
  (FPL)
publication_identifier:
  issn:
  - 1946-147X
publisher: Imperial College
status: public
title: Over effective hard real-time hardware tasks scheduling and allocation
type: conference
user_id: '398'
year: '2015'
...
---
_id: '37007'
abstract:
- lang: eng
  text: UML is widely applied for the specification and modeling of software and some
    studies have demonstrated that it is applicable for HW/SW codesign. However, in
    this area there is still a big gap from UML modeling to SystemC-based verification
    and synthesis environments. This paper presents an efficient approach to bridge
    this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework
    for the seamless integration of a customized SysML entry with code generation
    for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the
    SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate
    the applicability of our approach.
author:
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and
    Simulation of Combined HW/SW Systems. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>'
  apa: Mischkalla, F., He, D., &#38; Müller, W. (2010). Closing the Gap between UML-based
    Modeling and Simulation of Combined HW/SW Systems. <i>Proceedings of DATE’10</i>.
    2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE
    2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456990">https://doi.org/10.1109/DATE.2010.5456990</a>
  bibtex: '@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing
    the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems},
    DOI={<a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian
    and He, Da and Müller, Wolfgang}, year={2010} }'
  chicago: 'Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between
    UML-Based Modeling and Simulation of Combined HW/SW Systems.” In <i>Proceedings
    of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456990">https://doi.org/10.1109/DATE.2010.5456990</a>.'
  ieee: 'F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling
    and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation
    &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi:
    <a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>.'
  mla: Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and
    Simulation of Combined HW/SW Systems.” <i>Proceedings of DATE’10</i>, IEEE, 2010,
    doi:<a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>.
  short: 'F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden,
    2010.'
conference:
  location: Dresden
  name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:12:35Z
date_updated: 2023-01-17T09:12:44Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456990
keyword:
- Unified modeling language
- Field programmable gate arrays
- Bridges
- Helium
- Real time systems
- Operating systems
- Documentation
- Application software
- XML
- Space exploration
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW
  Systems
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37009'
abstract:
- lang: eng
  text: Today, mobile and embedded real time systems have to cope with the migration
    and allocation of multiple software tasks running on top of a real time operating
    system (RTOS) residing on one or several processors. For scaling of each task
    set and processor configuration, instruction set simulation and worst case timing
    analysis are typically applied. This paper presents a complementary approach for
    the verification of RTOS properties based on an abstract RTOS-Model in SystemC.
    We apply IEEE P1850 PSL for which we present an approach and first experiences
    for the assertion-based verification of RTOS properties.
author:
- first_name: Marcio F. S.
  full_name: Oliveira, Marcio F. S.
  last_name: Oliveira
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties.
    In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>'
  apa: Oliveira, M. F. S., Zabel, H., &#38; Müller, W. (2010). Assertion-Based Verification
    of RTOS Properties. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38;
    Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5457130">https://doi.org/10.1109/DATE.2010.5457130</a>
  bibtex: '@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based
    Verification of RTOS Properties}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio
    F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }'
  chicago: 'Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based
    Verification of RTOS Properties.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE,
    2010. <a href="https://doi.org/10.1109/DATE.2010.5457130">https://doi.org/10.1109/DATE.2010.5457130</a>.'
  ieee: 'M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification
    of RTOS Properties,” presented at the 2010 Design, Automation &#38; Test in Europe
    Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>.'
  mla: Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>.
  short: 'M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE,
    Dresden, 2010.'
conference:
  location: Dresden
  name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:15:10Z
date_updated: 2023-01-17T09:15:18Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457130
keyword:
- Operating systems
- Real time systems
- Timing
- Hardware
- Analytical models
- Embedded software
- Software systems
- Processor scheduling
- Software performance
- Performance analysis
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publisher: IEEE
status: public
title: Assertion-Based Verification of RTOS Properties
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37040'
abstract:
- lang: eng
  text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
    step design process which is a trade-off between timing accuracy of the used models
    and correct estimation of the final timing performance. The use of an RTOS on
    the target platform is mandatory in the case real-time properties must be guaranteed.
    Thus, the question is when the RTOS must be introduced in this step by step refinement
    process. This paper proposes a four-level RTOS-aware refinement methodology that,
    starting from an untimed TLM SystemC description of the whole system, progressively
    introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
    till to obtain an accurate model of the final platform, where SW tasks run upon
    an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
    Each refinement level allows the designer to estimate more and more accurate timing
    properties, thus anticipating design decisions without being constrained to leave
    timing analysis to the final step of the refinement. The effectiveness of the
    methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Giuseppe
  full_name: Di Guglielmo, Giuseppe
  last_name: Di Guglielmo
- first_name: Franco
  full_name: Fummi, Franco
  last_name: Fummi
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Graziano
  full_name: Pravadelli, Graziano
  last_name: Pravadelli
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
citation:
  ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
    Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>'
  apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38;
    Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings
    of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>
  bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
    title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
    Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
    Graziano and Xie, Tao}, year={2010} }'
  chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
    Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
    Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>.'
  ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
    “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
    Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden,
    2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.'
  mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.
  short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
    in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:47:29Z
date_updated: 2023-01-17T10:47:37Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37053'
abstract:
- lang: eng
  text: Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent
    Software (HdS) like drivers, operating systems, and firmware. For early estimation
    and verification, the application of SystemC in combination with Instruction Set
    Simulators and Software Emulators like QEMU is widely accepted. In this article,
    we present an advanced design flow for HW, (RT)OS and HdS refinement and verification
    with focus on the transition from abstract RTOS verification to full system RTOS/HdS
    emulation. In the context of assertion-based verification, we introduce a set
    of generic real-time properties which can be reused and verified at different
    abstraction levels and discuss their application. The properties are presented
    by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS
    models.
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Marcio F.
  full_name: da S. Oliveira, Marcio F.
  last_name: da S. Oliveira
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
citation:
  ama: 'Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time
    Properties for Hardware-Dependant Software. In: <i>Proceedings of HLDVT2010</i>.
    IEEE; 2010.'
  apa: Müller, W., da S. Oliveira, M. F., Zabel, H., &#38; Becker, M. (2010). Verification
    of Real-Time Properties for Hardware-Dependant Software. <i>Proceedings of HLDVT2010</i>.
    IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim,
    FL, USA.
  bibtex: '@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification
    of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings
    of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira,
    Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }'
  chicago: Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker.
    “Verification of Real-Time Properties for Hardware-Dependant Software.” In <i>Proceedings
    of HLDVT2010</i>. IEEE, 2010.
  ieee: W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of
    Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International
    High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.
  mla: Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant
    Software.” <i>Proceedings of HLDVT2010</i>, IEEE, 2010.
  short: 'W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of
    HLDVT2010, IEEE, 2010.'
conference:
  location: Anaheim, FL, USA
  name: IEEE International High Level Design Validation and Test Workshop (HLDVT)
date_created: 2023-01-17T11:28:26Z
date_updated: 2023-01-17T11:28:30Z
department:
- _id: '672'
keyword:
- Hardware
- Microprogramming
- Application software
- Timing
- Protocols
- Virtual prototyping
- Real time systems
- Sampling methods
- Operating systems
- Emulation
language:
- iso: eng
publication: Proceedings of HLDVT2010
publication_identifier:
  eisbn:
  - 978-1-4244-7806-4
publisher: IEEE
status: public
title: Verification of Real-Time Properties for Hardware-Dependant Software
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37039'
abstract:
- lang: eng
  text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
    step design process which is a trade-off between timing accuracy of the used models
    and correct estimation of the final timing performance. The use of an RTOS on
    the target platform is mandatory in the case real-time properties must be guaranteed.
    Thus, the question is when the RTOS must be introduced in this step by step refinement
    process. This paper proposes a four-level RTOS-aware refinement methodology that,
    starting from an untimed TLM SystemC description of the whole system, progressively
    introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
    till to obtain an accurate model of the final platform, where SW tasks run upon
    an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
    Each refinement level allows the designer to estimate more and more accurate timing
    properties, thus anticipating design decisions without being constrained to leave
    timing analysis to the final step of the refinement. The effectiveness of the
    methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Giuseppe
  full_name: Di Guglielmo, Giuseppe
  last_name: Di Guglielmo
- first_name: Franco
  full_name: Fummi, Franco
  last_name: Fummi
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Graziano
  full_name: Pravadelli, Graziano
  last_name: Pravadelli
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
citation:
  ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
    Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>'
  apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38;
    Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings
    of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>
  bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
    title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
    Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
    Graziano and Xie, Tao}, year={2010} }'
  chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
    Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
    Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>.'
  ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
    “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
    Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden,
    2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.'
  mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.
  short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
    in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:44:46Z
date_updated: 2025-03-12T16:39:17Z
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '10703'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable
    Computers. <i>ACM Transactions on Embedded Computing Systems</i>. 2009;9(1):8:1-8:33.
    doi:<a href="https://doi.org/10.1145/1596532.1596540">10.1145/1596532.1596540</a>'
  apa: 'Lübbers, E., &#38; Platzner, M. (2009). ReconOS: Multithreaded Programming
    for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>,
    <i>9</i>(1), 8:1-8:33. <a href="https://doi.org/10.1145/1596532.1596540">https://doi.org/10.1145/1596532.1596540</a>'
  bibtex: '@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming
    for Reconfigurable Computers}, volume={9}, DOI={<a href="https://doi.org/10.1145/1596532.1596540">10.1145/1596532.1596540</a>},
    number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers,
    Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }'
  chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming
    for Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i>
    9, no. 1 (2009): 8:1-8:33. <a href="https://doi.org/10.1145/1596532.1596540">https://doi.org/10.1145/1596532.1596540</a>.'
  ieee: 'E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable
    Computers,” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no.
    1, pp. 8:1-8:33, 2009.'
  mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for
    Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i>,
    vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:<a href="https://doi.org/10.1145/1596532.1596540">10.1145/1596532.1596540</a>.'
  short: E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9
    (2009) 8:1-8:33.
date_created: 2019-07-10T11:41:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1145/1596532.1596540
intvolume: '         9'
issue: '1'
keyword:
- Reconfigurable computing
- multithreading
- operating systems
language:
- iso: eng
page: 8:1-8:33
publication: ACM Transactions on Embedded Computing Systems
publication_identifier:
  issn:
  - 1539-9087
status: public
title: 'ReconOS: Multithreaded Programming for Reconfigurable Computers'
type: journal_article
user_id: '3118'
volume: 9
year: '2009'
...
---
_id: '37066'
abstract:
- lang: eng
  text: Today, mobile and embedded real-time systems have to cope with the migration
    and allocation of multiple software tasks running on top of a real-time operating
    system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations
    and timing analysis applies for fast and early estimation to configure it towards
    the individual needs of the application and environment. In this context, a high
    accuracy of the simulation compared to an instruction set simulation (ISS) is
    of key importance. In this paper, we investigate the accuracy of abstract RTOS
    simulation and compare it to ISS and the behavior of the physical system. We show
    that we can reach an increased accuracy of the simulation when we inject noise
    into the time model. Our results indicate that it is sufficient to inject uniformly
    distributed random time values to the RTOS real-time clock.
author:
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Zabel H, Müller W. Increased Accuracy through Noise Injection in Abstract
    RTOS Simulation. In: <i>Proceedings of DATE’09</i>. ; 2009. doi:<a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>'
  apa: Zabel, H., &#38; Müller, W. (2009). Increased Accuracy through Noise Injection
    in Abstract RTOS Simulation. <i>Proceedings of DATE’09</i>. Design, Automation
    &#38; Test in Europe Conference &#38; Exhibition. <a href="https://doi.org/10.1109/DATE.2009.5090925">https://doi.org/10.1109/DATE.2009.5090925</a>
  bibtex: '@inproceedings{Zabel_Müller_2009, place={Nice, France}, title={Increased
    Accuracy through Noise Injection in Abstract RTOS Simulation}, DOI={<a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>},
    booktitle={Proceedings of DATE’09}, author={Zabel, Henning and Müller, Wolfgang},
    year={2009} }'
  chicago: Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise
    Injection in Abstract RTOS Simulation.” In <i>Proceedings of DATE’09</i>. Nice,
    France, 2009. <a href="https://doi.org/10.1109/DATE.2009.5090925">https://doi.org/10.1109/DATE.2009.5090925</a>.
  ieee: 'H. Zabel and W. Müller, “Increased Accuracy through Noise Injection in Abstract
    RTOS Simulation,” presented at the Design, Automation &#38; Test in Europe Conference
    &#38; Exhibition, 2009, doi: <a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>.'
  mla: Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise Injection
    in Abstract RTOS Simulation.” <i>Proceedings of DATE’09</i>, 2009, doi:<a href="https://doi.org/10.1109/DATE.2009.5090925">10.1109/DATE.2009.5090925</a>.
  short: 'H. Zabel, W. Müller, in: Proceedings of DATE’09, Nice, France, 2009.'
conference:
  name: Design, Automation & Test in Europe Conference & Exhibition
date_created: 2023-01-17T11:51:44Z
date_updated: 2023-01-17T11:51:48Z
department:
- _id: '672'
doi: 10.1109/DATE.2009.5090925
keyword:
- Timing
- Analytical models
- Clocks
- Performance analysis
- Scheduling
- Operating systems
- Delay
- Real time systems
- Application software
- Context modeling
language:
- iso: eng
place: Nice, France
publication: Proceedings of DATE'09
publication_identifier:
  isbn:
  - 978-1-4244-3781-8
status: public
title: Increased Accuracy through Noise Injection in Abstract RTOS Simulation
type: conference
user_id: '5786'
year: '2009'
...
---
_id: '39032'
abstract:
- lang: eng
  text: Executable UML models are nowadays gaining interest in embedded systems design.
    This domain is strongly devoted to the modeling of reactive behavior using StateChart
    variants. In this context, the direct execution of UML state machines is an interesting
    alternative to native code generation approaches since it significantly increases
    portability. However, fully featured UML 2.0 State Machines may contain a broad
    set of features with complex execution semantics that differ significantly from
    other StateChart variants. This makes their direct execution complex and inefficient.
    In this paper, we demonstrate how such state machines can be represented using
    a small subset of the UML state machine features that enables efficient execution.
    We describe the necessary model transformations in terms of graph transformations
    and discuss the underlying semantics and implications for execution.
author:
- first_name: Tim
  full_name: Schattkowsky, Tim
  last_name: Schattkowsky
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Schattkowsky T, Müller W. Transformation of UML State Machines for Direct
    Execution. In: <i>Proceedings of VL/HCC 05</i>. ; 2005. doi:<a href="https://doi.org/10.1109/VLHCC.2005.64">10.1109/VLHCC.2005.64</a>'
  apa: Schattkowsky, T., &#38; Müller, W. (2005). Transformation of UML State Machines
    for Direct Execution. <i>Proceedings of VL/HCC 05</i>. <a href="https://doi.org/10.1109/VLHCC.2005.64">https://doi.org/10.1109/VLHCC.2005.64</a>
  bibtex: '@inproceedings{Schattkowsky_Müller_2005, place={Dallas, TX, USA}, title={Transformation
    of UML State Machines for Direct Execution}, DOI={<a href="https://doi.org/10.1109/VLHCC.2005.64">10.1109/VLHCC.2005.64</a>},
    booktitle={Proceedings of VL/HCC 05}, author={Schattkowsky, Tim and Müller, Wolfgang},
    year={2005} }'
  chicago: Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines
    for Direct Execution.” In <i>Proceedings of VL/HCC 05</i>. Dallas, TX, USA, 2005.
    <a href="https://doi.org/10.1109/VLHCC.2005.64">https://doi.org/10.1109/VLHCC.2005.64</a>.
  ieee: 'T. Schattkowsky and W. Müller, “Transformation of UML State Machines for
    Direct Execution,” 2005, doi: <a href="https://doi.org/10.1109/VLHCC.2005.64">10.1109/VLHCC.2005.64</a>.'
  mla: Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines
    for Direct Execution.” <i>Proceedings of VL/HCC 05</i>, 2005, doi:<a href="https://doi.org/10.1109/VLHCC.2005.64">10.1109/VLHCC.2005.64</a>.
  short: 'T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA,
    2005.'
date_created: 2023-01-24T08:18:10Z
date_updated: 2023-01-24T08:18:27Z
department:
- _id: '672'
doi: 10.1109/VLHCC.2005.64
keyword:
- Unified modeling language
- Software design
- Virtual machining
- Embedded system
- Programming
- Documentation
- Hardware
- Computer languages
- Operating systems
- Runtime
language:
- iso: eng
place: Dallas, TX, USA
publication: Proceedings of VL/HCC 05
publication_identifier:
  isbn:
  - 0-7695-2443-5
status: public
title: Transformation of UML State Machines for Direct Execution
type: conference
user_id: '5786'
year: '2005'
...