@inproceedings{17202,
  author       = {{Vollmer, Anna-Lisa and Grizou, Jonathan and Lopes, Manuel and Rohlfing, Katharina and Oudeyer, Pierre-Yves}},
  booktitle    = {{2014 Joint IEEE International Conference on Development and Learning and on Epigenetic Robotics}},
  isbn         = {{978-1-4799-7540-2}},
  keywords     = {{interaction, communication, co-construction, interaction protocols}},
  pages        = {{208 -- 215}},
  publisher    = {{IEEE}},
  title        = {{{Studying the Co-Construction of Interaction Protocols in Collaborative Tasks with Humans}}},
  year         = {{2014}},
}

@inproceedings{36922,
  abstract     = {{In this paper we present an approach for the self reconfiguration of distributed micro-controllers for increased fault tolerance. Based on a modified distributed system topology utilizing a time division multiple access (TDMA) protocol, i.e., Flex Ray, we present a self-organized distributed coordinator concept which performs the self-reconfiguration in the case of node failures. We introduce a distributed coordinator, which utilizes redundant slots in the Flex Ray communication schedule and combines messages in configured protocol frames and slots to avoid a complete bus restart. As such, the self-reconfiguration is realized by means of predetermined information about resulting changes in the communication dependencies and (re-)assignments determined in the design phase. To retrieve the necessary information, we present an analytical approach, which determines a combined solution for the initial configuration and all possible reconfigurations for the remaining nodes of the Flex Ray network in case of node failures. Hence, through this method we can design self-reconfiguring network-based systems enabling the handling of node failures for an increased fault tolerance.}},
  author       = {{Klobedanz, Kay and Müller, Wolfgang and Rettberg, Achim}},
  keywords     = {{Real time systems, Fault tolerant systems, Schedules, Protocols, Redundancy, Delay}},
  publisher    = {{IEEE}},
  title        = {{{An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems}}},
  doi          = {{10.1109/ISORCW.2012.41}},
  year         = {{2012}},
}

@inproceedings{37006,
  abstract     = {{In this paper we present an approach for the configuration and reconfiguration of FlexRay networks to increase their fault tolerance. To guarantee a correct and deterministic system behavior, the FlexRay specification does not allow a reconfiguration of the schedapproachule during run time. To avoid the necessity of a complete bus restart in case of a node failure, we propose a reconfiguration using redundant slots in the schedule and/or combine messages in existing frames and slots, to compensate node failures and increase robustness. Our approach supports the developer to increase the fault tolerance of the system during the design phase. It is a heuristic, which, additionally to a determined initial configuration, calculates possible reconfigurations for the remaining nodes of the FlexRay network in case of a node failure, to keep the system working properly. An evaluation by means of realistic safety-critical automotive real-time systems revealed that it determines valid reconfigurations for up to 80% of possible individual node failures. In summary, our approach offers major support for the developer of FlexRay networks since the results provide helpful feedback about reconfiguration capabilities. In an iterative design process these information can be used to determine and optimize valid reconfigurations.}},
  author       = {{Klobedanz, Kay and König, Andreas and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE'11}},
  keywords     = {{Schedules, Fault tolerant systems, Redundancy, Protocols, Automotive engineering, Genetic algorithms}},
  location     = {{Grenoble, France}},
  publisher    = {{IEEE}},
  title        = {{{A Reconfiguration Approach for Faul-Tolerant FlexRay Networks}}},
  doi          = {{10.1109/DATE.2011.5763022}},
  year         = {{2011}},
}

@inproceedings{37056,
  abstract     = {{In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to reduce the memory requirements of such backup nodes, we distribute redundant tasks over different nodes and propose the distributed coordinated migration of tasks of the defect ECU to the backup node at runtime. This approach enhances our former work in, where we extended the FlexRay bus schedule by redundant slots to consider changes in the communication/slot assignment and investigated and evaluated different solutions to migrate the redundant tasks to the backup node using the static and/or dynamic segment of the communication cycle for transmissions. We present the approach of distributed coordination for migration and communication instead of additional dedicated coordinator nodes to further increase the fault tolerance. With this approach we improve the safety of FlexRay networks by avoiding a possible single point of failure due to a dedicated coordinator node also minimizing the necessary time needed for a reconfiguration after an ECU failure. Furthermore, we reduce the overhead within the communication and the demand for additional hardware components.}},
  author       = {{Klobedanz, Kay and Defo, Gilles B. and Müller, Wolfgang and Kerstan, Timo}},
  booktitle    = {{Proceedings of SIES 2010}},
  keywords     = {{Fault tolerant systems, Protocols, Redundancy, Runtime, Payloads, Schedules}},
  title        = {{{Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks}}},
  doi          = {{10.1109/SIES.2010.5551384}},
  year         = {{2010}},
}

@inproceedings{37053,
  abstract     = {{Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.}},
  author       = {{Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}},
  booktitle    = {{Proceedings of HLDVT2010}},
  keywords     = {{Hardware, Microprogramming, Application software, Timing, Protocols, Virtual prototyping, Real time systems, Sampling methods, Operating systems, Emulation}},
  location     = {{Anaheim, FL, USA}},
  publisher    = {{IEEE}},
  title        = {{{Verification of Real-Time Properties for Hardware-Dependant Software}}},
  year         = {{2010}},
}

@inproceedings{38107,
  abstract     = {{TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML.}},
  author       = {{Großmann, Jürgen and Müller, Wolfgang}},
  booktitle    = {{Proc. of ISOLA 06}},
  isbn         = {{978-0-7695-3071-0}},
  keywords     = {{System testing, Software testing, Automotive engineering, Automatic testing, Machinery production industries, Protocols, Hardware design languages, Samarium, XML, Computer industry}},
  location     = {{Paphos, Cyprus}},
  title        = {{{A Formal Behavioral Semantics for TestML}}},
  doi          = {{10.1109/ISoLA.2006.37}},
  year         = {{2006}},
}

@inproceedings{39071,
  abstract     = {{The interconnection of software components is a key to enabling collaborative work. However, technology differences and security barriers like firewalls often hinder establishing collaborative infrastructures between enterprises or even within a single enterprise. We introduce a peer-to-peer based network infrastructure that transparently overcomes these problems using relay and routing mechanisms as well as different underlying transport protocols. We discuss the application of this technology to interconnect Web services.}},
  author       = {{Schattkowsky, Tim and Loeser, Chris and Müller, Wolfgang}},
  booktitle    = {{Proceedings of AINA2004}},
  isbn         = {{0-7695-2051-0}},
  keywords     = {{Peer to peer computing, Web services, Intelligent networks, Routing, Relays, Simple object access protocol, Collaborative work, Transport protocols, Network address translation, Java}},
  location     = {{Fukuoka, Japan }},
  publisher    = {{IEEE}},
  title        = {{{Peer-To-Peer Technology for Interconnecting Web Services in Heterogeneous Networks}}},
  doi          = {{10.1109/AINA.2004.1283977}},
  year         = {{2004}},
}

@inproceedings{39403,
  abstract     = {{The Unified Modeling Language (UML) has received wide acceptance as a standard language in the field of software specification by means of different diagram types. In a recent version of UML, the textual Object Constraint Language (OCL) was introduced to support specification of constraints for UML models. But OCL currently does not provide sufficient means to specify constraints over the dynamic behavior of a model. This article presents an OCL extension that is consistent with current OCL and enables modelers to specify state-related time-bounded constraints. We consider the case study of a flexible manufacturing system and identify typical real-time constraints. The constraints are presented in our temporal OCL extension as well as in temporal logic formulae. For general application, we define a semantics of our OCL extension by means of a time-bounded temporal logic based on Computational Tree Logic (CTL).}},
  author       = {{Flake, Stephan and Müller, Wolfgang}},
  booktitle    = {{Proceedings of HICSS-35}},
  isbn         = {{0-7695-1435-9}},
  keywords     = {{Unified modeling language, Logic, Formal verification, Real time systems, Programming profession, Vehicle dynamics, Software standards, Flexible manufacturing systems, Electronics industry, Protocols}},
  location     = {{Big Island, HI, USA }},
  title        = {{{Specification of Real-Time Properties for UML Models}}},
  doi          = {{10.1109/HICSS.2002.994469}},
  year         = {{2002}},
}

@inproceedings{39541,
  abstract     = {{We investigate a translation of SDL diagrams into the complete visual representation of Pictorial Janus (PJ) programs in order to analyze the specification by visual debugging and animation. We additionally introduce timing concepts to PJ (Timed PJ) for a mapping of the SDL timing statements. The concepts transforming SDL interaction and process diagrams into Timed PJ are outlined by an example sketching the transformation of an Ethernet CSMA/CD protocol specification.}},
  author       = {{Lehrenfeld, Georg and Müller, Wolfgang and Tahedl, C.}},
  booktitle    = {{Proceedings of Symposium on Visual Languages}},
  isbn         = {{0-8186-7045-2}},
  keywords     = {{Animation, Timing, Debugging, Ethernet networks, Multiaccess communication, Protocols, Computer languages, Prototypes, Environmental management, Visualization}},
  title        = {{{Transforming SDL Diagrams Into a Complete Visual Representation}}},
  doi          = {{10.1109/VL.1995.520803}},
  year         = {{1995}},
}

@inproceedings{39538,
  abstract     = {{This article discusses the application of Pictorial Janus (PJ) for the rapid development and analysis of protocols by animation and complete visualization. In order to make PJ applicable in the context of hardware description we first extend PJ by timing facilities (Timed PJ) and introduce an approach for integrating VHDL models into this visual framework preserving the simulation semantics of VHDL. We finally give the example of the specification and animation of a non interlocked protocol.}},
  author       = {{Müller, Wolfgang and Lehrenfeld, Georg and Tahedl, C.}},
  booktitle    = {{Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair}},
  isbn         = {{4-930813-67-0}},
  keywords     = {{Animation, Protocols, Timing, Computer languages, Electronic mail, Context modeling, Visualization, Control systems, Flow graphs, Trademarks}},
  title        = {{{Complete Visual Specification and Animations of Protocols}}},
  doi          = {{10.1109/ASPDAC.1995.486383}},
  year         = {{1995}},
}