@inproceedings{10779,
  author       = {{Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}},
  booktitle    = {{25th International Conference on Field Programmable Logic and Applications (FPL)}},
  issn         = {{1946-147X}},
  keywords     = {{embedded systems, field programmable gate arrays, operating systems (computers), scheduling, μC/OS-II, FPGAs, OS foundation, SafeRTOS, Xenomai, chip utilization ration, complex time constraints, embedded systems, hard real-time hardware task allocation, hard real-time hardware task scheduling, hardware-software real-time operating systems, partially reconfigurable field-programmable gate arrays, resource constraints, safety-critical RTOS, Field programmable gate arrays, Hardware, Job shop scheduling, Real-time systems, Shape, Software}},
  publisher    = {{Imperial College}},
  title        = {{{Over effective hard real-time hardware tasks scheduling and allocation}}},
  doi          = {{10.1109/FPL.2015.7293994}},
  year         = {{2015}},
}

@inproceedings{36922,
  abstract     = {{In this paper we present an approach for the self reconfiguration of distributed micro-controllers for increased fault tolerance. Based on a modified distributed system topology utilizing a time division multiple access (TDMA) protocol, i.e., Flex Ray, we present a self-organized distributed coordinator concept which performs the self-reconfiguration in the case of node failures. We introduce a distributed coordinator, which utilizes redundant slots in the Flex Ray communication schedule and combines messages in configured protocol frames and slots to avoid a complete bus restart. As such, the self-reconfiguration is realized by means of predetermined information about resulting changes in the communication dependencies and (re-)assignments determined in the design phase. To retrieve the necessary information, we present an analytical approach, which determines a combined solution for the initial configuration and all possible reconfigurations for the remaining nodes of the Flex Ray network in case of node failures. Hence, through this method we can design self-reconfiguring network-based systems enabling the handling of node failures for an increased fault tolerance.}},
  author       = {{Klobedanz, Kay and Müller, Wolfgang and Rettberg, Achim}},
  keywords     = {{Real time systems, Fault tolerant systems, Schedules, Protocols, Redundancy, Delay}},
  publisher    = {{IEEE}},
  title        = {{{An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems}}},
  doi          = {{10.1109/ISORCW.2012.41}},
  year         = {{2012}},
}

@inproceedings{37007,
  abstract     = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}},
  author       = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}},
  doi          = {{10.1109/DATE.2010.5456990}},
  year         = {{2010}},
}

@inproceedings{37009,
  abstract     = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}},
  author       = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Assertion-Based Verification of RTOS Properties}}},
  doi          = {{10.1109/DATE.2010.5457130}},
  year         = {{2010}},
}

@inproceedings{37040,
  abstract     = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}},
  author       = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}},
  doi          = {{10.1109/DATE.2010.5456965}},
  year         = {{2010}},
}

@inproceedings{37053,
  abstract     = {{Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.}},
  author       = {{Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}},
  booktitle    = {{Proceedings of HLDVT2010}},
  keywords     = {{Hardware, Microprogramming, Application software, Timing, Protocols, Virtual prototyping, Real time systems, Sampling methods, Operating systems, Emulation}},
  location     = {{Anaheim, FL, USA}},
  publisher    = {{IEEE}},
  title        = {{{Verification of Real-Time Properties for Hardware-Dependant Software}}},
  year         = {{2010}},
}

@inproceedings{37039,
  abstract     = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}},
  author       = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}},
  doi          = {{10.1109/DATE.2010.5456965}},
  year         = {{2010}},
}

@inproceedings{37066,
  abstract     = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.}},
  author       = {{Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE'09}},
  isbn         = {{978-1-4244-3781-8}},
  keywords     = {{Timing, Analytical models, Clocks, Performance analysis, Scheduling, Operating systems, Delay, Real time systems, Application software, Context modeling}},
  title        = {{{Increased Accuracy through Noise Injection in Abstract RTOS Simulation}}},
  doi          = {{10.1109/DATE.2009.5090925}},
  year         = {{2009}},
}

@inproceedings{39029,
  abstract     = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}},
  author       = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}},
  booktitle    = {{Proceedings of DATE’05}},
  isbn         = {{0-7695-2288-2}},
  keywords     = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}},
  publisher    = {{IEEE}},
  title        = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}},
  doi          = {{10.1109/DATE.2005.20}},
  year         = {{2005}},
}

@inproceedings{39069,
  abstract     = {{We present the syntax and semantics of a past- and future-oriented temporal extension of the Object Constraint Language (OCL). Our extension supports designers to express time-bounded properties over a state-oriented UML model of a system under development. The semantics is formally defined over the system states of a mathematical object model. Additionally, we present a mapping to Clocked Linear Temporal Logic (Clocked LTL) formulae, which is the basis for further application in verification with model checking. We demonstrate the applicability of the approach by the example of a buffer specification in the context of a production system.}},
  author       = {{Flake, Stephan and Müller, Wolfgang}},
  booktitle    = {{Proceedings of SEFM´04}},
  isbn         = {{0-7695-2222-X}},
  keywords     = {{Unified modeling language, Logic, Clocks, Boolean functions, Application software, Time factors, Real time systems, Formal verification, Buffer storage, Software packages}},
  publisher    = {{IEEE}},
  title        = {{{Past- and Future-Oriented Time-Bound Temporal Properties with OCL}}},
  doi          = {{10.1109/SEFM.2004.1347516}},
  year         = {{2004}},
}

@inproceedings{39403,
  abstract     = {{The Unified Modeling Language (UML) has received wide acceptance as a standard language in the field of software specification by means of different diagram types. In a recent version of UML, the textual Object Constraint Language (OCL) was introduced to support specification of constraints for UML models. But OCL currently does not provide sufficient means to specify constraints over the dynamic behavior of a model. This article presents an OCL extension that is consistent with current OCL and enables modelers to specify state-related time-bounded constraints. We consider the case study of a flexible manufacturing system and identify typical real-time constraints. The constraints are presented in our temporal OCL extension as well as in temporal logic formulae. For general application, we define a semantics of our OCL extension by means of a time-bounded temporal logic based on Computational Tree Logic (CTL).}},
  author       = {{Flake, Stephan and Müller, Wolfgang}},
  booktitle    = {{Proceedings of HICSS-35}},
  isbn         = {{0-7695-1435-9}},
  keywords     = {{Unified modeling language, Logic, Formal verification, Real time systems, Programming profession, Vehicle dynamics, Software standards, Flexible manufacturing systems, Electronics industry, Protocols}},
  location     = {{Big Island, HI, USA }},
  title        = {{{Specification of Real-Time Properties for UML Models}}},
  doi          = {{10.1109/HICSS.2002.994469}},
  year         = {{2002}},
}

@inproceedings{39502,
  abstract     = {{The authors present a new approach to an interactive design and analysis environment for visual languages. The main components, i.e., editor animator and interpreter are introduced. Their interactions are being investigated emphasizing the interpreter-animator interaction and defining an interface supporting different levels of automation. The interpreter performs the executions on a logical level and triggers the animator. The interactive animation provides a very high degree of liveness since it is based on the tight integration of the animator and editor. The proposed architecture permits the distributed implementation of a system for real-time animation. Their concepts are validated by the implementation of a debugging environment for the complete visual programming language Pictorial Janus.}},
  author       = {{Dücker, M. and Lehrenfeld, Georg and Müller, Wolfgang and Tahedl, C.}},
  booktitle    = {{ Proceedings International Conference and Workshop on Engineering of Computer-Based Systems}},
  isbn         = {{0-8186-7889-5}},
  keywords     = {{Real time systems, Animation, Debugging, Automation, Computer languages, Timing, Environmental management, Programming environments, Visualization, Multimedia systems}},
  location     = {{Monterey, CA, USA }},
  title        = {{{A Generic System for Interactive Real--Time Animation}}},
  doi          = {{10.1109/ECBS.1997.581876}},
  year         = {{1997}},
}