---
_id: '10779'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Omar
full_name: Kermia, Omar
last_name: Kermia
- first_name: Abdelhakim
full_name: Khouas, Abdelhakim
last_name: Khouas
citation:
ama: 'Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks
scheduling and allocation. In: 25th International Conference on Field Programmable
Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994'
apa: Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time
hardware tasks scheduling and allocation. In 25th International Conference
on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994
bibtex: '@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard
real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994},
booktitle={25th International Conference on Field Programmable Logic and Applications
(FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar
and Khouas, Abdelhakim}, year={2015} }'
chicago: Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective
Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International
Conference on Field Programmable Logic and Applications (FPL). Imperial College,
2015. https://doi.org/10.1109/FPL.2015.7293994.
ieee: Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware
tasks scheduling and allocation,” in 25th International Conference on Field
Programmable Logic and Applications (FPL), 2015.
mla: Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling
and Allocation.” 25th International Conference on Field Programmable Logic
and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.
short: 'Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on
Field Programmable Logic and Applications (FPL), Imperial College, 2015.'
date_created: 2019-07-10T12:11:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPL.2015.7293994
extern: '1'
keyword:
- embedded systems
- field programmable gate arrays
- operating systems (computers)
- scheduling
- μC/OS-II
- FPGAs
- OS foundation
- SafeRTOS
- Xenomai
- chip utilization ration
- complex time constraints
- embedded systems
- hard real-time hardware task allocation
- hard real-time hardware task scheduling
- hardware-software real-time operating systems
- partially reconfigurable field-programmable gate arrays
- resource constraints
- safety-critical RTOS
- Field programmable gate arrays
- Hardware
- Job shop scheduling
- Real-time systems
- Shape
- Software
language:
- iso: eng
publication: 25th International Conference on Field Programmable Logic and Applications
(FPL)
publication_identifier:
issn:
- 1946-147X
publisher: Imperial College
status: public
title: Over effective hard real-time hardware tasks scheduling and allocation
type: conference
user_id: '398'
year: '2015'
...
---
_id: '36922'
abstract:
- lang: eng
text: In this paper we present an approach for the self reconfiguration of distributed
micro-controllers for increased fault tolerance. Based on a modified distributed
system topology utilizing a time division multiple access (TDMA) protocol, i.e.,
Flex Ray, we present a self-organized distributed coordinator concept which performs
the self-reconfiguration in the case of node failures. We introduce a distributed
coordinator, which utilizes redundant slots in the Flex Ray communication schedule
and combines messages in configured protocol frames and slots to avoid a complete
bus restart. As such, the self-reconfiguration is realized by means of predetermined
information about resulting changes in the communication dependencies and (re-)assignments
determined in the design phase. To retrieve the necessary information, we present
an analytical approach, which determines a combined solution for the initial configuration
and all possible reconfigurations for the remaining nodes of the Flex Ray network
in case of node failures. Hence, through this method we can design self-reconfiguring
network-based systems enabling the handling of node failures for an increased
fault tolerance.
author:
- first_name: Kay
full_name: Klobedanz, Kay
last_name: Klobedanz
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Achim
full_name: Rettberg, Achim
last_name: Rettberg
citation:
ama: 'Klobedanz K, Müller W, Rettberg A. An Approach for Self-Reconfiguring and
Fault-Tolerant Distributed Real-Time Systems. In: IEEE; 2012. doi:10.1109/ISORCW.2012.41'
apa: Klobedanz, K., Müller, W., & Rettberg, A. (2012). An Approach for Self-Reconfiguring
and Fault-Tolerant Distributed Real-Time Systems. IEEE 15th International
Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing
Workshops. https://doi.org/10.1109/ISORCW.2012.41
bibtex: '@inproceedings{Klobedanz_Müller_Rettberg_2012, place={Shenzhen, China },
title={An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time
Systems}, DOI={10.1109/ISORCW.2012.41},
publisher={IEEE}, author={Klobedanz, Kay and Müller, Wolfgang and Rettberg, Achim},
year={2012} }'
chicago: 'Klobedanz, Kay, Wolfgang Müller, and Achim Rettberg. “An Approach for
Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems.” Shenzhen,
China : IEEE, 2012. https://doi.org/10.1109/ISORCW.2012.41.'
ieee: 'K. Klobedanz, W. Müller, and A. Rettberg, “An Approach for Self-Reconfiguring
and Fault-Tolerant Distributed Real-Time Systems,” presented at the IEEE 15th
International Symposium on Object/Component/Service-Oriented Real-Time Distributed
Computing Workshops, 2012, doi: 10.1109/ISORCW.2012.41.'
mla: Klobedanz, Kay, et al. An Approach for Self-Reconfiguring and Fault-Tolerant
Distributed Real-Time Systems. IEEE, 2012, doi:10.1109/ISORCW.2012.41.
short: 'K. Klobedanz, W. Müller, A. Rettberg, in: IEEE, Shenzhen, China , 2012.'
conference:
name: IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time
Distributed Computing Workshops
date_created: 2023-01-16T12:23:50Z
date_updated: 2023-01-16T12:25:33Z
department:
- _id: '672'
doi: 10.1109/ISORCW.2012.41
keyword:
- Real time systems
- Fault tolerant systems
- Schedules
- Protocols
- Redundancy
- Delay
language:
- iso: eng
place: 'Shenzhen, China '
publication_identifier:
eisbn:
- 978-0-7695-4669-8
publisher: IEEE
status: public
title: An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time
Systems
type: conference
user_id: '5786'
year: '2012'
...
---
_id: '37007'
abstract:
- lang: eng
text: UML is widely applied for the specification and modeling of software and some
studies have demonstrated that it is applicable for HW/SW codesign. However, in
this area there is still a big gap from UML modeling to SystemC-based verification
and synthesis environments. This paper presents an efficient approach to bridge
this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework
for the seamless integration of a customized SysML entry with code generation
for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the
SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate
the applicability of our approach.
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Da
full_name: He, Da
last_name: He
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and
Simulation of Combined HW/SW Systems. In: Proceedings of DATE’10. IEEE;
2010. doi:10.1109/DATE.2010.5456990'
apa: Mischkalla, F., He, D., & Müller, W. (2010). Closing the Gap between UML-based
Modeling and Simulation of Combined HW/SW Systems. Proceedings of DATE’10.
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE
2010), Dresden. https://doi.org/10.1109/DATE.2010.5456990
bibtex: '@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing
the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems},
DOI={10.1109/DATE.2010.5456990},
booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian
and He, Da and Müller, Wolfgang}, year={2010} }'
chicago: 'Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between
UML-Based Modeling and Simulation of Combined HW/SW Systems.” In Proceedings
of DATE’10. Dresden: IEEE, 2010. https://doi.org/10.1109/DATE.2010.5456990.'
ieee: 'F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling
and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation
& Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi:
10.1109/DATE.2010.5456990.'
mla: Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and
Simulation of Combined HW/SW Systems.” Proceedings of DATE’10, IEEE, 2010,
doi:10.1109/DATE.2010.5456990.
short: 'F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden,
2010.'
conference:
location: Dresden
name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:12:35Z
date_updated: 2023-01-17T09:12:44Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456990
keyword:
- Unified modeling language
- Field programmable gate arrays
- Bridges
- Helium
- Real time systems
- Operating systems
- Documentation
- Application software
- XML
- Space exploration
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
eisbn:
- 978-3-9810801-6-2
publisher: IEEE
status: public
title: Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW
Systems
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37009'
abstract:
- lang: eng
text: Today, mobile and embedded real time systems have to cope with the migration
and allocation of multiple software tasks running on top of a real time operating
system (RTOS) residing on one or several processors. For scaling of each task
set and processor configuration, instruction set simulation and worst case timing
analysis are typically applied. This paper presents a complementary approach for
the verification of RTOS properties based on an abstract RTOS-Model in SystemC.
We apply IEEE P1850 PSL for which we present an approach and first experiences
for the assertion-based verification of RTOS properties.
author:
- first_name: Marcio F. S.
full_name: Oliveira, Marcio F. S.
last_name: Oliveira
- first_name: Henning
full_name: Zabel, Henning
last_name: Zabel
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties.
In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5457130'
apa: Oliveira, M. F. S., Zabel, H., & Müller, W. (2010). Assertion-Based Verification
of RTOS Properties. Proceedings of DATE’10. 2010 Design, Automation &
Test in Europe Conference & Exhibition (DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5457130
bibtex: '@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based
Verification of RTOS Properties}, DOI={10.1109/DATE.2010.5457130},
booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio
F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }'
chicago: 'Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based
Verification of RTOS Properties.” In Proceedings of DATE’10. Dresden: IEEE,
2010. https://doi.org/10.1109/DATE.2010.5457130.'
ieee: 'M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification
of RTOS Properties,” presented at the 2010 Design, Automation & Test in Europe
Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5457130.'
mla: Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.”
Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5457130.
short: 'M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE,
Dresden, 2010.'
conference:
location: Dresden
name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:15:10Z
date_updated: 2023-01-17T09:15:18Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457130
keyword:
- Operating systems
- Real time systems
- Timing
- Hardware
- Analytical models
- Embedded software
- Software systems
- Processor scheduling
- Software performance
- Performance analysis
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publisher: IEEE
status: public
title: Assertion-Based Verification of RTOS Properties
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37040'
abstract:
- lang: eng
text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
step design process which is a trade-off between timing accuracy of the used models
and correct estimation of the final timing performance. The use of an RTOS on
the target platform is mandatory in the case real-time properties must be guaranteed.
Thus, the question is when the RTOS must be introduced in this step by step refinement
process. This paper proposes a four-level RTOS-aware refinement methodology that,
starting from an untimed TLM SystemC description of the whole system, progressively
introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
till to obtain an accurate model of the final platform, where SW tasks run upon
an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
Each refinement level allows the designer to estimate more and more accurate timing
properties, thus anticipating design decisions without being constrained to leave
timing analysis to the final step of the refinement. The effectiveness of the
methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Giuseppe
full_name: Di Guglielmo, Giuseppe
last_name: Di Guglielmo
- first_name: Franco
full_name: Fummi, Franco
last_name: Fummi
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Graziano
full_name: Pravadelli, Graziano
last_name: Pravadelli
- first_name: Tao
full_name: Xie, Tao
last_name: Xie
citation:
ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
Refinement for TLM2.0-based HW/SW Design. In: Proceedings of DATE’10. IEEE;
2010. doi:10.1109/DATE.2010.5456965'
apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &
Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. Proceedings
of DATE’10. Design, Automation & Test in Europe Conference & Exhibition
(DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5456965
bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={10.1109/DATE.2010.5456965},
booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
Graziano and Xie, Tao}, year={2010} }'
chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
Design.” In Proceedings of DATE’10. Dresden: IEEE, 2010. https://doi.org/10.1109/DATE.2010.5456965.'
ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
“RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden,
2010, doi: 10.1109/DATE.2010.5456965.'
mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5456965.
short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
location: Dresden
name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:47:29Z
date_updated: 2023-01-17T10:47:37Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
eisbn:
- 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37053'
abstract:
- lang: eng
text: Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent
Software (HdS) like drivers, operating systems, and firmware. For early estimation
and verification, the application of SystemC in combination with Instruction Set
Simulators and Software Emulators like QEMU is widely accepted. In this article,
we present an advanced design flow for HW, (RT)OS and HdS refinement and verification
with focus on the transition from abstract RTOS verification to full system RTOS/HdS
emulation. In the context of assertion-based verification, we introduce a set
of generic real-time properties which can be reused and verified at different
abstraction levels and discuss their application. The properties are presented
by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS
models.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Marcio F.
full_name: da S. Oliveira, Marcio F.
last_name: da S. Oliveira
- first_name: Henning
full_name: Zabel, Henning
last_name: Zabel
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
citation:
ama: 'Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time
Properties for Hardware-Dependant Software. In: Proceedings of HLDVT2010.
IEEE; 2010.'
apa: Müller, W., da S. Oliveira, M. F., Zabel, H., & Becker, M. (2010). Verification
of Real-Time Properties for Hardware-Dependant Software. Proceedings of HLDVT2010.
IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim,
FL, USA.
bibtex: '@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification
of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings
of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira,
Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }'
chicago: Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker.
“Verification of Real-Time Properties for Hardware-Dependant Software.” In Proceedings
of HLDVT2010. IEEE, 2010.
ieee: W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of
Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International
High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.
mla: Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant
Software.” Proceedings of HLDVT2010, IEEE, 2010.
short: 'W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of
HLDVT2010, IEEE, 2010.'
conference:
location: Anaheim, FL, USA
name: IEEE International High Level Design Validation and Test Workshop (HLDVT)
date_created: 2023-01-17T11:28:26Z
date_updated: 2023-01-17T11:28:30Z
department:
- _id: '672'
keyword:
- Hardware
- Microprogramming
- Application software
- Timing
- Protocols
- Virtual prototyping
- Real time systems
- Sampling methods
- Operating systems
- Emulation
language:
- iso: eng
publication: Proceedings of HLDVT2010
publication_identifier:
eisbn:
- 978-1-4244-7806-4
publisher: IEEE
status: public
title: Verification of Real-Time Properties for Hardware-Dependant Software
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37039'
abstract:
- lang: eng
text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
step design process which is a trade-off between timing accuracy of the used models
and correct estimation of the final timing performance. The use of an RTOS on
the target platform is mandatory in the case real-time properties must be guaranteed.
Thus, the question is when the RTOS must be introduced in this step by step refinement
process. This paper proposes a four-level RTOS-aware refinement methodology that,
starting from an untimed TLM SystemC description of the whole system, progressively
introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
till to obtain an accurate model of the final platform, where SW tasks run upon
an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
Each refinement level allows the designer to estimate more and more accurate timing
properties, thus anticipating design decisions without being constrained to leave
timing analysis to the final step of the refinement. The effectiveness of the
methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Giuseppe
full_name: Di Guglielmo, Giuseppe
last_name: Di Guglielmo
- first_name: Franco
full_name: Fummi, Franco
last_name: Fummi
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Graziano
full_name: Pravadelli, Graziano
last_name: Pravadelli
- first_name: Tao
full_name: Xie, Tao
last_name: Xie
citation:
ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
Refinement for TLM2.0-based HW/SW Design. In: Proceedings of DATE’10. IEEE;
2010. doi:10.1109/DATE.2010.5456965'
apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &
Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. Proceedings
of DATE’10. Design, Automation & Test in Europe Conference & Exhibition
(DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5456965
bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={10.1109/DATE.2010.5456965},
booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
Graziano and Xie, Tao}, year={2010} }'
chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
Design.” In Proceedings of DATE’10. Dresden: IEEE, 2010. https://doi.org/10.1109/DATE.2010.5456965.'
ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
“RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden,
2010, doi: 10.1109/DATE.2010.5456965.'
mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5456965.
short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
location: Dresden
name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:44:46Z
date_updated: 2025-03-12T16:39:17Z
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
eisbn:
- 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37066'
abstract:
- lang: eng
text: Today, mobile and embedded real-time systems have to cope with the migration
and allocation of multiple software tasks running on top of a real-time operating
system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations
and timing analysis applies for fast and early estimation to configure it towards
the individual needs of the application and environment. In this context, a high
accuracy of the simulation compared to an instruction set simulation (ISS) is
of key importance. In this paper, we investigate the accuracy of abstract RTOS
simulation and compare it to ISS and the behavior of the physical system. We show
that we can reach an increased accuracy of the simulation when we inject noise
into the time model. Our results indicate that it is sufficient to inject uniformly
distributed random time values to the RTOS real-time clock.
author:
- first_name: Henning
full_name: Zabel, Henning
last_name: Zabel
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Zabel H, Müller W. Increased Accuracy through Noise Injection in Abstract
RTOS Simulation. In: Proceedings of DATE’09. ; 2009. doi:10.1109/DATE.2009.5090925'
apa: Zabel, H., & Müller, W. (2009). Increased Accuracy through Noise Injection
in Abstract RTOS Simulation. Proceedings of DATE’09. Design, Automation
& Test in Europe Conference & Exhibition. https://doi.org/10.1109/DATE.2009.5090925
bibtex: '@inproceedings{Zabel_Müller_2009, place={Nice, France}, title={Increased
Accuracy through Noise Injection in Abstract RTOS Simulation}, DOI={10.1109/DATE.2009.5090925},
booktitle={Proceedings of DATE’09}, author={Zabel, Henning and Müller, Wolfgang},
year={2009} }'
chicago: Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise
Injection in Abstract RTOS Simulation.” In Proceedings of DATE’09. Nice,
France, 2009. https://doi.org/10.1109/DATE.2009.5090925.
ieee: 'H. Zabel and W. Müller, “Increased Accuracy through Noise Injection in Abstract
RTOS Simulation,” presented at the Design, Automation & Test in Europe Conference
& Exhibition, 2009, doi: 10.1109/DATE.2009.5090925.'
mla: Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise Injection
in Abstract RTOS Simulation.” Proceedings of DATE’09, 2009, doi:10.1109/DATE.2009.5090925.
short: 'H. Zabel, W. Müller, in: Proceedings of DATE’09, Nice, France, 2009.'
conference:
name: Design, Automation & Test in Europe Conference & Exhibition
date_created: 2023-01-17T11:51:44Z
date_updated: 2023-01-17T11:51:48Z
department:
- _id: '672'
doi: 10.1109/DATE.2009.5090925
keyword:
- Timing
- Analytical models
- Clocks
- Performance analysis
- Scheduling
- Operating systems
- Delay
- Real time systems
- Application software
- Context modeling
language:
- iso: eng
place: Nice, France
publication: Proceedings of DATE'09
publication_identifier:
isbn:
- 978-1-4244-3781-8
status: public
title: Increased Accuracy through Noise Injection in Abstract RTOS Simulation
type: conference
user_id: '5786'
year: '2009'
...
---
_id: '39029'
abstract:
- lang: eng
text: UML 2.0 provides a rich set of diagrams for systems documentation and specification.
Much effort has been undertaken to employ different aspects of UML for multiple
domains, mainly in the area of software systems. Considering the area of electronic
design automation, however, we currently see only very few approaches which investigate
UML for hardware design and hardware/software co-design. We present an approach
for executable UML closing the gap from system specification to its model-based
execution on reconfigurable hardware. For this purpose, we present our abstract
execution platform (AEP), which is based on a virtual machine running an executable
UML subset for embedded software and reconfigurable hardware. This subset combines
UML 2.0 classes, state-machines and sequence diagrams for a complete system specification.
We describe how these binary encoded UML specifications can be directly executed
and give the implementation of such a virtual machine on a Virtex II FPGA. Finally,
we present evaluation results comparing the AEP implementation with C code on
a C167 microcontroller.
author:
- first_name: Tim
full_name: Schattkowsky, Tim
last_name: Schattkowsky
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Achim
full_name: Rettberg, Achim
last_name: Rettberg
citation:
ama: 'Schattkowsky T, Müller W, Rettberg A. A Model-Based Approach for Executable
Specification on Reconfigurable Hardware. In: Proceedings of DATE’05. IEEE;
2005. doi:10.1109/DATE.2005.20'
apa: Schattkowsky, T., Müller, W., & Rettberg, A. (2005). A Model-Based Approach
for Executable Specification on Reconfigurable Hardware. Proceedings of DATE’05.
https://doi.org/10.1109/DATE.2005.20
bibtex: '@inproceedings{Schattkowsky_Müller_Rettberg_2005, place={Munich, Germany
}, title={A Model-Based Approach for Executable Specification on Reconfigurable
Hardware}, DOI={10.1109/DATE.2005.20},
booktitle={Proceedings of DATE’05}, publisher={IEEE}, author={Schattkowsky, Tim
and Müller, Wolfgang and Rettberg, Achim}, year={2005} }'
chicago: 'Schattkowsky, Tim, Wolfgang Müller, and Achim Rettberg. “A Model-Based
Approach for Executable Specification on Reconfigurable Hardware.” In Proceedings
of DATE’05. Munich, Germany : IEEE, 2005. https://doi.org/10.1109/DATE.2005.20.'
ieee: 'T. Schattkowsky, W. Müller, and A. Rettberg, “A Model-Based Approach for
Executable Specification on Reconfigurable Hardware,” 2005, doi: 10.1109/DATE.2005.20.'
mla: Schattkowsky, Tim, et al. “A Model-Based Approach for Executable Specification
on Reconfigurable Hardware.” Proceedings of DATE’05, IEEE, 2005, doi:10.1109/DATE.2005.20.
short: 'T. Schattkowsky, W. Müller, A. Rettberg, in: Proceedings of DATE’05, IEEE,
Munich, Germany , 2005.'
date_created: 2023-01-24T08:10:40Z
date_updated: 2023-01-24T08:10:44Z
department:
- _id: '672'
doi: 10.1109/DATE.2005.20
keyword:
- Hardware
- Unified modeling language
- Virtual machining
- Object oriented modeling
- Field programmable gate arrays
- Java
- Microcontrollers
- Embedded software
- Real time systems
- Documentation
language:
- iso: eng
place: 'Munich, Germany '
publication: Proceedings of DATE’05
publication_identifier:
isbn:
- 0-7695-2288-2
publisher: IEEE
status: public
title: A Model-Based Approach for Executable Specification on Reconfigurable Hardware
type: conference
user_id: '5786'
year: '2005'
...
---
_id: '39069'
abstract:
- lang: eng
text: We present the syntax and semantics of a past- and future-oriented temporal
extension of the Object Constraint Language (OCL). Our extension supports designers
to express time-bounded properties over a state-oriented UML model of a system
under development. The semantics is formally defined over the system states of
a mathematical object model. Additionally, we present a mapping to Clocked Linear
Temporal Logic (Clocked LTL) formulae, which is the basis for further application
in verification with model checking. We demonstrate the applicability of the approach
by the example of a buffer specification in the context of a production system.
author:
- first_name: Stephan
full_name: Flake, Stephan
last_name: Flake
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Flake S, Müller W. Past- and Future-Oriented Time-Bound Temporal Properties
with OCL. In: Proceedings of SEFM´04. IEEE; 2004. doi:10.1109/SEFM.2004.1347516'
apa: Flake, S., & Müller, W. (2004). Past- and Future-Oriented Time-Bound Temporal
Properties with OCL. Proceedings of SEFM´04. Proceedings of the Second
International Conference on Software Engineering and Formal Methods. https://doi.org/10.1109/SEFM.2004.1347516
bibtex: '@inproceedings{Flake_Müller_2004, place={Beijing, China}, title={Past-
and Future-Oriented Time-Bound Temporal Properties with OCL}, DOI={10.1109/SEFM.2004.1347516},
booktitle={Proceedings of SEFM´04}, publisher={IEEE}, author={Flake, Stephan and
Müller, Wolfgang}, year={2004} }'
chicago: 'Flake, Stephan, and Wolfgang Müller. “Past- and Future-Oriented Time-Bound
Temporal Properties with OCL.” In Proceedings of SEFM´04. Beijing, China:
IEEE, 2004. https://doi.org/10.1109/SEFM.2004.1347516.'
ieee: 'S. Flake and W. Müller, “Past- and Future-Oriented Time-Bound Temporal Properties
with OCL,” presented at the Proceedings of the Second International Conference
on Software Engineering and Formal Methods, 2004, doi: 10.1109/SEFM.2004.1347516.'
mla: Flake, Stephan, and Wolfgang Müller. “Past- and Future-Oriented Time-Bound
Temporal Properties with OCL.” Proceedings of SEFM´04, IEEE, 2004, doi:10.1109/SEFM.2004.1347516.
short: 'S. Flake, W. Müller, in: Proceedings of SEFM´04, IEEE, Beijing, China, 2004.'
conference:
name: ' Proceedings of the Second International Conference on Software Engineering
and Formal Methods'
date_created: 2023-01-24T09:03:36Z
date_updated: 2023-01-24T09:03:41Z
department:
- _id: '672'
doi: 10.1109/SEFM.2004.1347516
keyword:
- Unified modeling language
- Logic
- Clocks
- Boolean functions
- Application software
- Time factors
- Real time systems
- Formal verification
- Buffer storage
- Software packages
language:
- iso: eng
place: Beijing, China
publication: Proceedings of SEFM´04
publication_identifier:
isbn:
- 0-7695-2222-X
publisher: IEEE
status: public
title: Past- and Future-Oriented Time-Bound Temporal Properties with OCL
type: conference
user_id: '5786'
year: '2004'
...
---
_id: '39403'
abstract:
- lang: eng
text: The Unified Modeling Language (UML) has received wide acceptance as a standard
language in the field of software specification by means of different diagram
types. In a recent version of UML, the textual Object Constraint Language (OCL)
was introduced to support specification of constraints for UML models. But OCL
currently does not provide sufficient means to specify constraints over the dynamic
behavior of a model. This article presents an OCL extension that is consistent
with current OCL and enables modelers to specify state-related time-bounded constraints.
We consider the case study of a flexible manufacturing system and identify typical
real-time constraints. The constraints are presented in our temporal OCL extension
as well as in temporal logic formulae. For general application, we define a semantics
of our OCL extension by means of a time-bounded temporal logic based on Computational
Tree Logic (CTL).
author:
- first_name: Stephan
full_name: Flake, Stephan
last_name: Flake
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Flake S, Müller W. Specification of Real-Time Properties for UML Models. In:
Proceedings of HICSS-35. ; 2002. doi:10.1109/HICSS.2002.994469'
apa: Flake, S., & Müller, W. (2002). Specification of Real-Time Properties for
UML Models. Proceedings of HICSS-35. Proceedings of the 35th Annual Hawaii
International Conference on System Sciences, Big Island, HI, USA . https://doi.org/10.1109/HICSS.2002.994469
bibtex: '@inproceedings{Flake_Müller_2002, place={Big Island, HI, USA }, title={Specification
of Real-Time Properties for UML Models}, DOI={10.1109/HICSS.2002.994469},
booktitle={Proceedings of HICSS-35}, author={Flake, Stephan and Müller, Wolfgang},
year={2002} }'
chicago: Flake, Stephan, and Wolfgang Müller. “Specification of Real-Time Properties
for UML Models.” In Proceedings of HICSS-35. Big Island, HI, USA , 2002.
https://doi.org/10.1109/HICSS.2002.994469.
ieee: 'S. Flake and W. Müller, “Specification of Real-Time Properties for UML Models,”
presented at the Proceedings of the 35th Annual Hawaii International Conference
on System Sciences, Big Island, HI, USA , 2002, doi: 10.1109/HICSS.2002.994469.'
mla: Flake, Stephan, and Wolfgang Müller. “Specification of Real-Time Properties
for UML Models.” Proceedings of HICSS-35, 2002, doi:10.1109/HICSS.2002.994469.
short: 'S. Flake, W. Müller, in: Proceedings of HICSS-35, Big Island, HI, USA ,
2002.'
conference:
location: 'Big Island, HI, USA '
name: Proceedings of the 35th Annual Hawaii International Conference on System Sciences
date_created: 2023-01-24T10:22:12Z
date_updated: 2023-01-24T10:22:16Z
department:
- _id: '672'
doi: 10.1109/HICSS.2002.994469
keyword:
- Unified modeling language
- Logic
- Formal verification
- Real time systems
- Programming profession
- Vehicle dynamics
- Software standards
- Flexible manufacturing systems
- Electronics industry
- Protocols
language:
- iso: eng
place: 'Big Island, HI, USA '
publication: Proceedings of HICSS-35
publication_identifier:
isbn:
- 0-7695-1435-9
status: public
title: Specification of Real-Time Properties for UML Models
type: conference
user_id: '5786'
year: '2002'
...
---
_id: '39502'
abstract:
- lang: eng
text: The authors present a new approach to an interactive design and analysis environment
for visual languages. The main components, i.e., editor animator and interpreter
are introduced. Their interactions are being investigated emphasizing the interpreter-animator
interaction and defining an interface supporting different levels of automation.
The interpreter performs the executions on a logical level and triggers the animator.
The interactive animation provides a very high degree of liveness since it is
based on the tight integration of the animator and editor. The proposed architecture
permits the distributed implementation of a system for real-time animation. Their
concepts are validated by the implementation of a debugging environment for the
complete visual programming language Pictorial Janus.
author:
- first_name: M.
full_name: Dücker, M.
last_name: Dücker
- first_name: Georg
full_name: Lehrenfeld, Georg
last_name: Lehrenfeld
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: C.
full_name: Tahedl, C.
last_name: Tahedl
citation:
ama: 'Dücker M, Lehrenfeld G, Müller W, Tahedl C. A Generic System for Interactive
Real--Time Animation. In: Proceedings International Conference and Workshop
on Engineering of Computer-Based Systems. ; 1997. doi:10.1109/ECBS.1997.581876'
apa: Dücker, M., Lehrenfeld, G., Müller, W., & Tahedl, C. (1997). A Generic
System for Interactive Real--Time Animation. Proceedings International Conference
and Workshop on Engineering of Computer-Based Systems. https://doi.org/10.1109/ECBS.1997.581876
bibtex: '@inproceedings{Dücker_Lehrenfeld_Müller_Tahedl_1997, place={Monterey, CA,
USA }, title={A Generic System for Interactive Real--Time Animation}, DOI={10.1109/ECBS.1997.581876},
booktitle={ Proceedings International Conference and Workshop on Engineering of
Computer-Based Systems}, author={Dücker, M. and Lehrenfeld, Georg and Müller,
Wolfgang and Tahedl, C.}, year={1997} }'
chicago: Dücker, M., Georg Lehrenfeld, Wolfgang Müller, and C. Tahedl. “A Generic
System for Interactive Real--Time Animation.” In Proceedings International
Conference and Workshop on Engineering of Computer-Based Systems. Monterey,
CA, USA , 1997. https://doi.org/10.1109/ECBS.1997.581876.
ieee: 'M. Dücker, G. Lehrenfeld, W. Müller, and C. Tahedl, “A Generic System for
Interactive Real--Time Animation,” Monterey, CA, USA , 1997, doi: 10.1109/ECBS.1997.581876.'
mla: Dücker, M., et al. “A Generic System for Interactive Real--Time Animation.”
Proceedings International Conference and Workshop on Engineering of Computer-Based
Systems, 1997, doi:10.1109/ECBS.1997.581876.
short: 'M. Dücker, G. Lehrenfeld, W. Müller, C. Tahedl, in: Proceedings International
Conference and Workshop on Engineering of Computer-Based Systems, Monterey, CA,
USA , 1997.'
conference:
location: 'Monterey, CA, USA '
date_created: 2023-01-24T11:46:23Z
date_updated: 2023-01-24T11:46:28Z
department:
- _id: '672'
doi: 10.1109/ECBS.1997.581876
keyword:
- Real time systems
- Animation
- Debugging
- Automation
- Computer languages
- Timing
- Environmental management
- Programming environments
- Visualization
- Multimedia systems
language:
- iso: eng
place: 'Monterey, CA, USA '
publication: ' Proceedings International Conference and Workshop on Engineering of
Computer-Based Systems'
publication_identifier:
isbn:
- 0-8186-7889-5
status: public
title: A Generic System for Interactive Real--Time Animation
type: conference
user_id: '5786'
year: '1997'
...