[{"citation":{"apa":"Schwabe, T., Kress, C., Kruse, S., Weizel, M., Rhee, H., &#38; Scheytt, J. C. (2025). Forward-Biased Silicon Phase Shifter Modeling for Electronic-Photonic Co-Simulation and Validation in a 250 nm EPIC BiCMOS Technology. <i>Journal of Lightwave Technology</i>, <i>43</i>(1), 255–270. <a href=\"https://doi.org/10.1109/JLT.2024.3450949\">https://doi.org/10.1109/JLT.2024.3450949</a>","mla":"Schwabe, Tobias, et al. “Forward-Biased Silicon Phase Shifter Modeling for Electronic-Photonic Co-Simulation and Validation in a 250 Nm EPIC BiCMOS Technology.” <i>Journal of Lightwave Technology</i>, vol. 43, no. 1, 2025, pp. 255–70, doi:<a href=\"https://doi.org/10.1109/JLT.2024.3450949\">10.1109/JLT.2024.3450949</a>.","ieee":"T. Schwabe, C. Kress, S. Kruse, M. Weizel, H. Rhee, and J. C. Scheytt, “Forward-Biased Silicon Phase Shifter Modeling for Electronic-Photonic Co-Simulation and Validation in a 250 nm EPIC BiCMOS Technology,” <i>Journal of Lightwave Technology</i>, vol. 43, no. 1, pp. 255–270, 2025, doi: <a href=\"https://doi.org/10.1109/JLT.2024.3450949\">10.1109/JLT.2024.3450949</a>.","chicago":"Schwabe, Tobias, Christian Kress, Stephan Kruse, Maxim Weizel, Hanjo Rhee, and J. Christoph Scheytt. “Forward-Biased Silicon Phase Shifter Modeling for Electronic-Photonic Co-Simulation and Validation in a 250 Nm EPIC BiCMOS Technology.” <i>Journal of Lightwave Technology</i> 43, no. 1 (2025): 255–70. <a href=\"https://doi.org/10.1109/JLT.2024.3450949\">https://doi.org/10.1109/JLT.2024.3450949</a>.","ama":"Schwabe T, Kress C, Kruse S, Weizel M, Rhee H, Scheytt JC. Forward-Biased Silicon Phase Shifter Modeling for Electronic-Photonic Co-Simulation and Validation in a 250 nm EPIC BiCMOS Technology. <i>Journal of Lightwave Technology</i>. 2025;43(1):255-270. doi:<a href=\"https://doi.org/10.1109/JLT.2024.3450949\">10.1109/JLT.2024.3450949</a>","short":"T. Schwabe, C. Kress, S. Kruse, M. Weizel, H. Rhee, J.C. Scheytt, Journal of Lightwave Technology 43 (2025) 255–270.","bibtex":"@article{Schwabe_Kress_Kruse_Weizel_Rhee_Scheytt_2025, title={Forward-Biased Silicon Phase Shifter Modeling for Electronic-Photonic Co-Simulation and Validation in a 250 nm EPIC BiCMOS Technology}, volume={43}, DOI={<a href=\"https://doi.org/10.1109/JLT.2024.3450949\">10.1109/JLT.2024.3450949</a>}, number={1}, journal={Journal of Lightwave Technology}, author={Schwabe, Tobias and Kress, Christian and Kruse, Stephan and Weizel, Maxim and Rhee, Hanjo and Scheytt, J. Christoph}, year={2025}, pages={255–270} }"},"issue":"1","publication":"Journal of Lightwave Technology","date_created":"2025-11-27T07:14:34Z","department":[{"_id":"58"}],"type":"journal_article","keyword":["Integrated circuit modeling","Capacitance","Silicon","Modulation","Adaptation models","Semiconductor device modeling","Bandwidth","Data communication","electrooptical transmitter","equalization","free-carrier-plasma dispersion effect","modelling","optical modulator","phase shifter","silicon photonics"],"author":[{"id":"39217","full_name":"Schwabe, Tobias","first_name":"Tobias","last_name":"Schwabe"},{"id":"13256","first_name":"Christian","last_name":"Kress","orcid":"0000-0002-4403-2237","full_name":"Kress, Christian"},{"id":"38254","full_name":"Kruse, Stephan","last_name":"Kruse","first_name":"Stephan"},{"id":"44271","last_name":"Weizel","orcid":"0000-0003-2699-9839","first_name":"Maxim","full_name":"Weizel, Maxim"},{"first_name":"Hanjo","last_name":"Rhee","full_name":"Rhee, Hanjo"},{"id":"37144","full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","first_name":"J. Christoph"}],"title":"Forward-Biased Silicon Phase Shifter Modeling for Electronic-Photonic Co-Simulation and Validation in a 250 nm EPIC BiCMOS Technology","status":"public","year":"2025","intvolume":"        43","date_updated":"2025-11-27T07:16:01Z","_id":"62643","language":[{"iso":"eng"}],"page":"255-270","volume":43,"user_id":"38254","doi":"10.1109/JLT.2024.3450949"},{"department":[{"_id":"58"}],"keyword":["Optical attenuators","Equalizers","Phase shifters","Optical modulation","Electro-optic modulators","Optical amplifiers","Circuits","Silicon photonics","Optical saturation","Integrated circuit modeling","Data communication","equalization","electro-optical transmitter","silicon photonics","phase shifter","optical modulator","free-carrier plasma dispersion effect","driver architectures","biasing schemes"],"type":"journal_article","date_created":"2025-11-27T07:14:48Z","citation":{"chicago":"Schwabe, Tobias, Christian Kress, Babak Sadiye, Stephan Kruse, and J. Christoph Scheytt. “Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits.” <i>IEEE Access</i> 13 (2025): 192433–50. <a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">https://doi.org/10.1109/ACCESS.2025.3629385</a>.","short":"T. Schwabe, C. Kress, B. Sadiye, S. Kruse, J.C. Scheytt, IEEE Access 13 (2025) 192433–192450.","ieee":"T. Schwabe, C. Kress, B. Sadiye, S. Kruse, and J. C. Scheytt, “Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits,” <i>IEEE Access</i>, vol. 13, pp. 192433–192450, 2025, doi: <a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>.","apa":"Schwabe, T., Kress, C., Sadiye, B., Kruse, S., &#38; Scheytt, J. C. (2025). Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits. <i>IEEE Access</i>, <i>13</i>, 192433–192450. <a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">https://doi.org/10.1109/ACCESS.2025.3629385</a>","bibtex":"@article{Schwabe_Kress_Sadiye_Kruse_Scheytt_2025, title={Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits}, volume={13}, DOI={<a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>}, journal={IEEE Access}, author={Schwabe, Tobias and Kress, Christian and Sadiye, Babak and Kruse, Stephan and Scheytt, J. Christoph}, year={2025}, pages={192433–192450} }","ama":"Schwabe T, Kress C, Sadiye B, Kruse S, Scheytt JC. Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits. <i>IEEE Access</i>. 2025;13:192433-192450. doi:<a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>","mla":"Schwabe, Tobias, et al. “Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits.” <i>IEEE Access</i>, vol. 13, 2025, pp. 192433–50, doi:<a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>."},"publication":"IEEE Access","volume":13,"doi":"10.1109/ACCESS.2025.3629385","user_id":"38254","language":[{"iso":"eng"}],"_id":"62644","page":"192433-192450","intvolume":"        13","date_updated":"2025-11-27T07:16:06Z","author":[{"full_name":"Schwabe, Tobias","first_name":"Tobias","last_name":"Schwabe","id":"39217"},{"last_name":"Kress","first_name":"Christian","orcid":"0000-0002-4403-2237","full_name":"Kress, Christian","id":"13256"},{"id":"93634","first_name":"Babak","last_name":"Sadiye","full_name":"Sadiye, Babak"},{"full_name":"Kruse, Stephan","last_name":"Kruse","first_name":"Stephan","id":"38254"},{"full_name":"Scheytt, J. Christoph","last_name":"Scheytt","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","id":"37144"}],"year":"2025","title":"Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits","status":"public"},{"status":"public","user_id":"30525","publisher":"American Chemical Society (ACS)","_id":"58606","project":[{"name":"TRR 142: TRR 142 - Maßgeschneiderte nichtlineare Photonik: Von grundlegenden Konzepten zu funktionellen Strukturen","_id":"53"},{"name":"TRR 142 - A: TRR 142 - Project Area A","_id":"54"},{"name":"TRR 142 - B: TRR 142 - Project Area B","_id":"55"},{"_id":"170","name":"TRR 142 - B09: TRR 142 - Effiziente Erzeugung mit maßgeschneiderter optischer Phaselage der zweiten Harmonischen mittels Quasi-gebundener Zustände in GaAs Metaoberflächen (B09*)"},{"name":"TRR 142 - A08: TRR 142 - Nichtlineare Kopplung von Zwischenschicht-Exzitonen in van der Waals-Heterostrukturen an plasmonische und dielektrische Nanokavitäten (A08)","_id":"65"}],"quality_controlled":"1","citation":{"ieee":"A. Mathew <i>et al.</i>, “Nonreciprocal Metasurfaces with Epsilon-Near-Zero Materials,” <i>Nano Letters</i>, 2025, doi: <a href=\"https://doi.org/10.1021/acs.nanolett.4c06188\">10.1021/acs.nanolett.4c06188</a>.","apa":"Mathew, A., Aschwanden, R., Tripathi, A., Jangid, P., Sain, B., Zentgraf, T., &#38; Kruk, S. (2025). Nonreciprocal Metasurfaces with Epsilon-Near-Zero Materials. <i>Nano Letters</i>. <a href=\"https://doi.org/10.1021/acs.nanolett.4c06188\">https://doi.org/10.1021/acs.nanolett.4c06188</a>","mla":"Mathew, Albert, et al. “Nonreciprocal Metasurfaces with Epsilon-Near-Zero Materials.” <i>Nano Letters</i>, American Chemical Society (ACS), 2025, doi:<a href=\"https://doi.org/10.1021/acs.nanolett.4c06188\">10.1021/acs.nanolett.4c06188</a>.","bibtex":"@article{Mathew_Aschwanden_Tripathi_Jangid_Sain_Zentgraf_Kruk_2025, title={Nonreciprocal Metasurfaces with Epsilon-Near-Zero Materials}, DOI={<a href=\"https://doi.org/10.1021/acs.nanolett.4c06188\">10.1021/acs.nanolett.4c06188</a>}, journal={Nano Letters}, publisher={American Chemical Society (ACS)}, author={Mathew, Albert and Aschwanden, Rebecca and Tripathi, Aditya and Jangid, Piyush and Sain, Basudeb and Zentgraf, Thomas and Kruk, Sergey}, year={2025} }","ama":"Mathew A, Aschwanden R, Tripathi A, et al. Nonreciprocal Metasurfaces with Epsilon-Near-Zero Materials. <i>Nano Letters</i>. Published online 2025. doi:<a href=\"https://doi.org/10.1021/acs.nanolett.4c06188\">10.1021/acs.nanolett.4c06188</a>","short":"A. Mathew, R. Aschwanden, A. Tripathi, P. Jangid, B. Sain, T. Zentgraf, S. Kruk, Nano Letters (2025).","chicago":"Mathew, Albert, Rebecca Aschwanden, Aditya Tripathi, Piyush Jangid, Basudeb Sain, Thomas Zentgraf, and Sergey Kruk. “Nonreciprocal Metasurfaces with Epsilon-Near-Zero Materials.” <i>Nano Letters</i>, 2025. <a href=\"https://doi.org/10.1021/acs.nanolett.4c06188\">https://doi.org/10.1021/acs.nanolett.4c06188</a>."},"external_id":{"arxiv":["2501.11920"]},"article_type":"original","publication_status":"published","date_updated":"2026-04-20T05:06:06Z","publication_identifier":{"issn":["1530-6984","1530-6992"]},"author":[{"last_name":"Mathew","first_name":"Albert","full_name":"Mathew, Albert"},{"full_name":"Aschwanden, Rebecca","first_name":"Rebecca","last_name":"Aschwanden"},{"full_name":"Tripathi, Aditya","first_name":"Aditya","last_name":"Tripathi"},{"full_name":"Jangid, Piyush","first_name":"Piyush","last_name":"Jangid"},{"full_name":"Sain, Basudeb","last_name":"Sain","first_name":"Basudeb"},{"orcid":"0000-0002-8662-1101","first_name":"Thomas","last_name":"Zentgraf","full_name":"Zentgraf, Thomas","id":"30525"},{"last_name":"Kruk","first_name":"Sergey","full_name":"Kruk, Sergey"}],"title":"Nonreciprocal Metasurfaces with Epsilon-Near-Zero Materials","year":"2025","doi":"10.1021/acs.nanolett.4c06188","language":[{"iso":"eng"}],"main_file_link":[{"url":"https://pubs.acs.org/doi/full/10.1021/acs.nanolett.4c06188"}],"publication":"Nano Letters","department":[{"_id":"15"},{"_id":"230"},{"_id":"289"},{"_id":"623"}],"keyword":["metasurfaces","nanophotonics","nonreciprocity","optical isolators","silicon photonics"],"type":"journal_article","date_created":"2025-02-12T12:54:41Z"},{"citation":{"bibtex":"@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>}, publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }","ama":"Sprenger A. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn; 2023. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>","mla":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn, 2023, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>.","short":"A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023.","chicago":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>.","ieee":"A. Sprenger, <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023.","apa":"Sprenger, A. (2023). <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>"},"supervisor":[{"orcid":"0000-0002-3717-3939","first_name":"Sybille","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"place":"Paderborn","oa":"1","status":"public","page":"xi, 160","_id":"46482","publisher":"Universität Paderborn","user_id":"22707","extern":"1","abstract":[{"text":"Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem.\r\nWith modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty.","lang":"eng"},{"text":"Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei und fehlerhaft zu klassifizieren.","lang":"ger"}],"date_created":"2023-08-12T09:10:38Z","type":"dissertation","keyword":["Testantwortkompaktierung","Prozessvariation","Silicon Lifecycle Management"],"department":[{"_id":"48"}],"title":"Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen","year":"2023","author":[{"full_name":"Sprenger, Alexander","last_name":"Sprenger","orcid":"0000-0002-0775-7677","first_name":"Alexander","id":"22707"}],"publication_status":"published","date_updated":"2023-08-12T09:13:18Z","main_file_link":[{"url":"https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493","open_access":"1"}],"language":[{"iso":"ger"}],"doi":"10.17619/UNIPB/1-1787"}]