@article{11892, abstract = {{For an environment to be perceived as being smart, contextual information has to be gathered to adapt the system's behavior and its interface towards the user. Being a rich source of context information speech can be acquired unobtrusively by microphone arrays and then processed to extract information about the user and his environment. In this paper, a system for joint temporal segmentation, speaker localization, and identification is presented, which is supported by face identification from video data obtained from a steerable camera. Special attention is paid to latency aspects and online processing capabilities, as they are important for the application under investigation, namely ambient communication. It describes the vision of terminal-less, session-less and multi-modal telecommunication with remote partners, where the user can move freely within his home while the communication follows him. The speaker diarization serves as a context source, which has been integrated in a service-oriented middleware architecture and provided to the application to select the most appropriate I/O device and to steer the camera towards the speaker during ambient communication.}}, author = {{Schmalenstroeer, Joerg and Haeb-Umbach, Reinhold}}, journal = {{IEEE Journal of Selected Topics in Signal Processing}}, keywords = {{audio streaming, audio visual data streaming, context information speech, face identification, face recognition, image segmentation, middleware, multimodal telecommunication, online diarization, service oriented middleware architecture, sessionless telecommunication, software architecture, speaker identification, speaker localization, speaker recognition, steerable camera, telecommunication computing, temporal segmentation, terminal-less telecommunication, video streaming}}, number = {{5}}, pages = {{845--856}}, title = {{{Online Diarization of Streaming Audio-Visual Data for Smart Environments}}}, doi = {{10.1109/JSTSP.2010.2050519}}, volume = {{4}}, year = {{2010}}, } @inproceedings{37007, abstract = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}}, author = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}}, doi = {{10.1109/DATE.2010.5456990}}, year = {{2010}}, } @inproceedings{37009, abstract = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}}, author = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Assertion-Based Verification of RTOS Properties}}}, doi = {{10.1109/DATE.2010.5457130}}, year = {{2010}}, } @inproceedings{37011, abstract = {{Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study.}}, author = {{Klobedanz, Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10, Dresden}}, keywords = {{Timing, Programming, Automotive engineering, Application software, Hardware, Computer architecture, Communication system software, Software architecture, Delay, Software standards}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study}}}, doi = {{10.1109/DATE.2010.5457125}}, year = {{2010}}, } @inproceedings{37037, abstract = {{Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.}}, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{System testing, Automatic testing, Object oriented modeling, Classification tree analysis, Automotive engineering, Mathematical model, Embedded system, Control systems, Electronic equipment testing, Software testing}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{A Systematic Approach to Combined HW/SW System Test}}}, doi = {{10.1109/DATE.2010.5457186}}, year = {{2010}}, } @inproceedings{37053, abstract = {{Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.}}, author = {{Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}}, booktitle = {{Proceedings of HLDVT2010}}, keywords = {{Hardware, Microprogramming, Application software, Timing, Protocols, Virtual prototyping, Real time systems, Sampling methods, Operating systems, Emulation}}, location = {{Anaheim, FL, USA}}, publisher = {{IEEE}}, title = {{{Verification of Real-Time Properties for Hardware-Dependant Software}}}, year = {{2010}}, } @inproceedings{5625, abstract = {{The increasing availability and deployment of open source software in personal and commercial environments makes open source software highly appealing for hackers, and others who are interested in exploiting software vulnerabilities. This deployment has resulted in a debate ?full of religion? on the security of open source software compared to that of closed source software. However, beyond such arguments, only little quantitative analysis on this research issue has taken place. We discuss the state-of-the-art of the security debate and identify shortcomings. Based on these, we propose new metrics, which allows to answer the question to what extent the review process of open source and closed source development has helped to fix vulnerabilities. We illustrate the application of some of these metrics in a case study on OpenOffice (open source software) vs. Microsoft Office (closed source software).}}, author = {{Schryen, Guido and Kadura, Rouven}}, booktitle = {{24th Annual ACM Symposium on Applied Computing}}, keywords = {{Open source software, Closed source software, Security, Metrics}}, title = {{{Open Source vs. Closed Source Software: Towards Measuring Security}}}, year = {{2009}}, } @inproceedings{5647, abstract = {{Reviewing literature on open source and closed source security reveals that the discussion is often determined by biased attitudes toward one of these development styles. The discussion specifically lacks appropriate metrics, methodology and hard data. This paper contributes to solving this problem by analyzing and comparing published vulnerabilities of eight open source software and nine closed source software packages, all of which are widely deployed. Thereby, it provides an extensive empirical analysis of vulnerabilities in terms of mean time between vulnerability disclosures, the development of disclosure over time, and the severity of vulnerabilities, and allows for validating models provided in the literature. The investigation reveals that (a) the mean time between vulnerability disclosures was lower for open source software in half of the cases, while the other cases show no differences, (b) in contrast to literature assumption, 14 out of 17 software packages showed a significant linear or piecewise linear correlation between time and the number of published vulnerabilities, and (c) regarding the severity of vulnerabilities, no significant differences were found between open source and closed source.}}, author = {{Schryen, Guido}}, booktitle = {{15th Americas Conference on Information Systems}}, keywords = {{Vulnerabilities, security, open source software, closed source software, empirical comparison}}, title = {{{Security of open source and closed source software: An empirical comparison of published vulnerabilities}}}, year = {{2009}}, } @inbook{33814, abstract = {{Rapidly rising system complexity has created a growing productivity gap in the design of electronic systems. One critical component is Hardware-dependent Software (HdS), the importance of which is often underestimated. In this chap- ter, we introduce HdS and illustrate its role in the overall system design context. We also provide a brief overview and define a basic HdS terminology and con- clude with a brief outlook over the following chapters in this book.}}, author = {{Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}}, booktitle = {{Hardware Dependent Software - Principles and Practice}}, editor = {{Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}}, isbn = {{978-1-4020-9435-4}}, keywords = {{Hardware-dependent Software, Systems Complexity, Productivity Gap}}, pages = {{1--14}}, publisher = {{Springer Verlag}}, title = {{{Hardware-dependent Software - Introduction and Overview}}}, doi = {{10.1007/978-1-4020-9436-1_1}}, year = {{2009}}, } @inproceedings{37067, abstract = {{IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these descriptions at the XML level can be time-consuming and error-prone. In this paper, we show that the UML can be consistently applied as an efficient and comprehensible frontend for IP-XACT-based IP description and integration. For this, we present an IP-XACT UML profile that enables UML-based descriptions covering the same information as a corresponding IP-XACT description. This enables the automated generation of IP-XACT component and design descriptions from respective UML models. In particular, it also allows the integration of existing IPs with UML. To illustrate our approach, we present an application example based on the IBM PowerPC Evaluation Kit.}}, author = {{Schattkowsky, Tim and Xie, Tao and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE'09}}, isbn = {{978-1-4244-3781-8}}, keywords = {{Unified modeling language, XML, Power system modeling, Application software, Master-slave, Power system management, Acceleration, Scattering, Software engineering, Software standards}}, publisher = {{IEEE}}, title = {{{A UML Frontend for IP-XACT-based IP Management}}}, doi = {{10.1109/DATE.2009.5090664}}, year = {{2009}}, } @inproceedings{37066, abstract = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.}}, author = {{Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE'09}}, isbn = {{978-1-4244-3781-8}}, keywords = {{Timing, Analytical models, Clocks, Performance analysis, Scheduling, Operating systems, Delay, Real time systems, Application software, Context modeling}}, title = {{{Increased Accuracy through Noise Injection in Abstract RTOS Simulation}}}, doi = {{10.1109/DATE.2009.5090925}}, year = {{2009}}, } @inproceedings{17272, abstract = {{In developmental research, tutoring behavior has been identified as scaffolding infants' learning processes. It has been defined in terms of child-directed speech (Motherese), child-directed motion (Motionese), and contingency. In the field of developmental robotics, research often assumes that in human-robot interaction (HRI), robots are treated similar to infants, because their immature cognitive capabilities benefit from this behavior. However, according to our knowledge, it has barely been studied whether this is true and how exactly humans alter their behavior towards a robotic interaction partner. In this paper, we present results concerning the acceptance of a robotic agent in a social learning scenario obtained via comparison to adults and 8-11 months old infants in equal conditions. These results constitute an important empirical basis for making use of tutoring behavior in social robotics. In our study, we performed a detailed multimodal analysis of HRI in a tutoring situation using the example of a robot simulation equipped with a bottom-up saliency-based attention model. Our results reveal significant differences in hand movement velocity, motion pauses, range of motion, and eye gaze suggesting that for example adults decrease their hand movement velocity in an Adult-Child Interaction (ACI), opposed to an Adult-Adult Interaction (AAI) and this decrease is even higher in the Adult-Robot Interaction (ARI). We also found important differences between ACI and ARI in how the behavior is modified over time as the interaction unfolds. These findings indicate the necessity of integrating top-down feedback structures into a bottom-up system for robots to be fully accepted as interaction partners.}}, author = {{Vollmer, Anna-Lisa and Lohan, Katrin Solveig and Fischer, Kerstin and Nagai, Yukie and Pitsch, Karola and Fritsch, Jannik and Rohlfing, Katharina and Wrede, Britta}}, booktitle = {{Development and Learning, 2009. ICDL 2009. IEEE 8th International Conference on Development and Learning}}, keywords = {{robot simulation, hand movement velocity, robotic interaction partner, robotic agent, robot-directed interaction, multimodal analysis, Motionese, Motherese, intelligent tutoring systems, immature cognitive capability, human computer interaction, eye gaze, child-directed speech, child-directed motion, bottom-up system, bottom-up saliency-based attention model, adult-robot interaction, adult-child interaction, adult-adult interaction, human-robot interaction, action learning, social learning scenario, social robotics, software agents, top-down feedback structures, tutoring behavior}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{People modify their tutoring behavior in robot-directed interaction for action learning}}}, doi = {{10.1109/DEVLRN.2009.5175516}}, year = {{2009}}, } @inproceedings{38107, abstract = {{TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML.}}, author = {{Großmann, Jürgen and Müller, Wolfgang}}, booktitle = {{Proc. of ISOLA 06}}, isbn = {{978-0-7695-3071-0}}, keywords = {{System testing, Software testing, Automotive engineering, Automatic testing, Machinery production industries, Protocols, Hardware design languages, Samarium, XML, Computer industry}}, location = {{Paphos, Cyprus}}, title = {{{A Formal Behavioral Semantics for TestML}}}, doi = {{10.1109/ISoLA.2006.37}}, year = {{2006}}, } @inproceedings{39029, abstract = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}}, booktitle = {{Proceedings of DATE’05}}, isbn = {{0-7695-2288-2}}, keywords = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}}, publisher = {{IEEE}}, title = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}}, doi = {{10.1109/DATE.2005.20}}, year = {{2005}}, } @inproceedings{39030, abstract = {{StateCharts are well accepted for embedded systems specification for various applications. However, for the specification of complex systems they have several limitations. In this article, we present a novel approach to efficiently execute an UML 2.0 subset for embedded real- time systems implementation with focus on hardware interrupts, software exceptions, and timeouts. We introduce a UML Virtual Machine, which directly executes sequence diagrams, which are embedded into hierarchically structured state transition diagrams. Whereas state diagrams are directly executed as Embedded State Machines (ESMs), sequence diagrams are translated into UVM Bytecode. The final UVM execution is performed by the interaction of the ESM and the Bytecode Interpreter. Due to our completely model- based approach, the UVM runtime kernel is easily adaptable and scalable to different scheduling and memory management strategies.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of ISNG 05}}, keywords = {{UML, Executable Models, Hardware/Software Co-design, Virtual Machine, Embedded Systems}}, title = {{{A UML Virtual Machine for Embedded Systems}}}, year = {{2005}}, } @inproceedings{39032, abstract = {{Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of VL/HCC 05}}, isbn = {{0-7695-2443-5}}, keywords = {{Unified modeling language, Software design, Virtual machining, Embedded system, Programming, Documentation, Hardware, Computer languages, Operating systems, Runtime}}, title = {{{Transformation of UML State Machines for Direct Execution}}}, doi = {{10.1109/VLHCC.2005.64}}, year = {{2005}}, } @inproceedings{39069, abstract = {{We present the syntax and semantics of a past- and future-oriented temporal extension of the Object Constraint Language (OCL). Our extension supports designers to express time-bounded properties over a state-oriented UML model of a system under development. The semantics is formally defined over the system states of a mathematical object model. Additionally, we present a mapping to Clocked Linear Temporal Logic (Clocked LTL) formulae, which is the basis for further application in verification with model checking. We demonstrate the applicability of the approach by the example of a buffer specification in the context of a production system.}}, author = {{Flake, Stephan and Müller, Wolfgang}}, booktitle = {{Proceedings of SEFM´04}}, isbn = {{0-7695-2222-X}}, keywords = {{Unified modeling language, Logic, Clocks, Boolean functions, Application software, Time factors, Real time systems, Formal verification, Buffer storage, Software packages}}, publisher = {{IEEE}}, title = {{{Past- and Future-Oriented Time-Bound Temporal Properties with OCL}}}, doi = {{10.1109/SEFM.2004.1347516}}, year = {{2004}}, } @inproceedings{39382, abstract = {{We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, wait for, par, and try statements as they are introduced in SpecC. We present our definition in form of distributed abstract state machine (ASM) rules strictly following the lines of the SpecC Language Reference Manual. We mainly see our formal semantics in three application areas. First, it is a concise, unambiguous description for documentation and standardization. Second, it applies as a high-level, pseudo code-oriented specification for the implementation of a SpecC simulator. Finally, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets.}}, author = {{Müller, Wolfgang and Dömer, Rainer and Gerstlauer, Andreas}}, booktitle = {{Proceedings of the ISSS02}}, isbn = {{1-58113-576-9}}, keywords = {{Standardization, Kernel, Permission, Formal verification, Logic functions, Documentation, Reasoning about programs, Specification languages, Formal specifications, Software systems}}, title = {{{The Formal Execution Semantics of SpecC}}}, doi = {{10.1145/581199.581234 }}, year = {{2002}}, } @inproceedings{39403, abstract = {{The Unified Modeling Language (UML) has received wide acceptance as a standard language in the field of software specification by means of different diagram types. In a recent version of UML, the textual Object Constraint Language (OCL) was introduced to support specification of constraints for UML models. But OCL currently does not provide sufficient means to specify constraints over the dynamic behavior of a model. This article presents an OCL extension that is consistent with current OCL and enables modelers to specify state-related time-bounded constraints. We consider the case study of a flexible manufacturing system and identify typical real-time constraints. The constraints are presented in our temporal OCL extension as well as in temporal logic formulae. For general application, we define a semantics of our OCL extension by means of a time-bounded temporal logic based on Computational Tree Logic (CTL).}}, author = {{Flake, Stephan and Müller, Wolfgang}}, booktitle = {{Proceedings of HICSS-35}}, isbn = {{0-7695-1435-9}}, keywords = {{Unified modeling language, Logic, Formal verification, Real time systems, Programming profession, Vehicle dynamics, Software standards, Flexible manufacturing systems, Electronics industry, Protocols}}, location = {{Big Island, HI, USA }}, title = {{{Specification of Real-Time Properties for UML Models}}}, doi = {{10.1109/HICSS.2002.994469}}, year = {{2002}}, } @article{39925, author = {{Goser, K. and Hilleringmann, Ulrich and Rueckert, U. and Schumacher, K.}}, issn = {{0272-1732}}, journal = {{IEEE Micro}}, keywords = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}}, number = {{6}}, pages = {{28--44}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{VLSI technologies for artificial neural networks}}}, doi = {{10.1109/40.42985}}, volume = {{9}}, year = {{2002}}, }