[{"language":[{"iso":"eng"}],"keyword":["Approximate computing","Design space exploration","Accelerator synthesis"],"department":[{"_id":"78"}],"user_id":"64665","_id":"22309","status":"public","abstract":[{"text":"Approximate computing (AC) has acquired significant maturity in recent years as a promising approach to obtain energy and area-efficient hardware. Automated approximate accelerator synthesis involves a great deal of complexity on the size of design space which exponentially grows with the number of possible approximations. Design space exploration of approximate accelerator synthesis is usually targeted via heuristic-based search methods. The majority of existing frameworks prune a large part of the design space using a greedy-based approach to keep the problem tractable. Therefore, they result in inferior solutions since many potential solutions are neglected in the pruning process without the possibility of backtracking of removed approximate instances. In this paper, we address the aforementioned issue by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based search algorithm, in the context of automated synthesis of approximate accelerators. This enables the synthesis frameworks to deeply subsamples the design space of approximate accelerator synthesis toward most promising approximate instances based on the required performance goals, i.e., power consumption, area, or/and delay. We investigated the challenges of providing an efficient open-source framework that benefits analytical and search-based approximation techniques simultaneously to both speed up the synthesis runtime and improve the quality of obtained results. Besides, we studied the utilization of machine learning algorithms to improve the performance of several critical steps, i.e., accelerator quality testing, in the synthesis framework. The proposed framework can help the community to rapidly generate efficient approximate accelerators in a reasonable runtime.","lang":"eng"}],"publication":"Proceedings of IEEE Computer Society Annual Symposium on VLSI","type":"conference","conference":{"name":"IEEE Computer Society Annual Symposium on VLSI","start_date":"2021-07-07","end_date":"2021-07-09","location":"Tampa, Florida USA (Virtual)"},"title":"MCTS-Based Synthesis Towards Efficient Approximate Accelerators","date_created":"2021-06-14T14:05:17Z","author":[{"full_name":"Awais, Muhammad","id":"64665","last_name":"Awais","orcid":"https://orcid.org/0000-0003-4148-2969","first_name":"Muhammad"},{"last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","date_updated":"2022-01-06T06:55:31Z","page":"384-389","citation":{"ama":"Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators. In: <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>. IEEE; 2021:384-389.","chicago":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” In <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, 384–89. IEEE, 2021.","ieee":"M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, Tampa, Florida USA (Virtual), 2021, pp. 384–389.","short":"M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, 2021, pp. 384–389.","bibtex":"@inproceedings{Awais_Platzner_2021, title={MCTS-Based Synthesis Towards Efficient Approximate Accelerators}, booktitle={Proceedings of IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE}, author={Awais, Muhammad and Platzner, Marco}, year={2021}, pages={384–389} }","mla":"Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient Approximate Accelerators.” <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, IEEE, 2021, pp. 384–89.","apa":"Awais, M., &#38; Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient Approximate Accelerators. <i>Proceedings of IEEE Computer Society Annual Symposium on VLSI</i>, 384–389."},"year":"2021"},{"title":"Jump Search: A Fast Technique for the Synthesis of Approximate Circuits","date_created":"2020-04-25T08:02:07Z","author":[{"first_name":"Linus Matthias","last_name":"Witschen","id":"49051","full_name":"Witschen, Linus Matthias"},{"last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","id":"61186","first_name":"Hassan"},{"full_name":"Artmann, Matthias","last_name":"Artmann","first_name":"Matthias"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"date_updated":"2022-01-06T06:52:57Z","page":"2","citation":{"apa":"Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., &#38; Platzner, M. (n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. <i>Fourth Workshop on Approximate Computing (AxC 2019)</i>.","mla":"Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” <i>Fourth Workshop on Approximate Computing (AxC 2019)</i>.","bibtex":"@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }","short":"L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth Workshop on Approximate Computing (AxC 2019) (n.d.).","ieee":"L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” <i>Fourth Workshop on Approximate Computing (AxC 2019)</i>. .","chicago":"Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” <i>Fourth Workshop on Approximate Computing (AxC 2019)</i>, n.d.","ama":"Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. <i>Fourth Workshop on Approximate Computing (AxC 2019)</i>."},"year":"2019","has_accepted_license":"1","publication_status":"accepted","file_date_updated":"2020-04-25T08:00:35Z","language":[{"iso":"eng"}],"keyword":["Approximate computing","parameter selection","search space exploration","verification","circuit synthesis"],"ddc":["006"],"department":[{"_id":"78"}],"user_id":"49051","_id":"16853","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_name":"AxC19_paper_3.pdf","access_level":"closed","file_id":"16854","file_size":152806,"creator":"witschen","date_created":"2020-04-25T08:00:35Z","date_updated":"2020-04-25T08:00:35Z"}],"abstract":[{"text":"State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.","lang":"eng"}],"publication":"Fourth Workshop on Approximate Computing (AxC 2019)","type":"preprint"},{"status":"public","publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","type":"conference","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"language":[{"iso":"eng"}],"_id":"2200","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","place":"New York, NY, USA","year":"2011","page":"177-180","citation":{"chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>","apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180."},"publication_identifier":{"isbn":["978-1-4503-0554-9"]},"quality_controlled":"1","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","doi":"10.1145/1950413.1950448","publisher":"ACM","date_updated":"2023-09-26T13:45:04Z","date_created":"2018-04-03T15:08:13Z","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Kauschke, Michael","last_name":"Kauschke","first_name":"Michael"}]},{"department":[{"_id":"672"}],"user_id":"5786","_id":"37007","language":[{"iso":"eng"}],"keyword":["Unified modeling language","Field programmable gate arrays","Bridges","Helium","Real time systems","Operating systems","Documentation","Application software","XML","Space exploration"],"publication":"Proceedings of DATE’10","type":"conference","status":"public","abstract":[{"text":"UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.","lang":"eng"}],"date_created":"2023-01-17T09:12:35Z","author":[{"first_name":"Fabian","full_name":"Mischkalla, Fabian","last_name":"Mischkalla"},{"full_name":"He, Da","last_name":"He","first_name":"Da"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"date_updated":"2023-01-17T09:12:44Z","publisher":"IEEE","conference":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"},"doi":"10.1109/DATE.2010.5456990","title":"Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems","publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"citation":{"apa":"Mischkalla, F., He, D., &#38; Müller, W. (2010). Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>","mla":"Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>.","bibtex":"@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian and He, Da and Müller, Wolfgang}, year={2010} }","short":"F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","chicago":"Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>.","ieee":"F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>.","ama":"Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>"},"year":"2010","place":"Dresden"}]