---
_id: '22309'
abstract:
- lang: eng
text: Approximate computing (AC) has acquired significant maturity in recent years
as a promising approach to obtain energy and area-efficient hardware. Automated
approximate accelerator synthesis involves a great deal of complexity on the size
of design space which exponentially grows with the number of possible approximations.
Design space exploration of approximate accelerator synthesis is usually targeted
via heuristic-based search methods. The majority of existing frameworks prune
a large part of the design space using a greedy-based approach to keep the problem
tractable. Therefore, they result in inferior solutions since many potential solutions
are neglected in the pruning process without the possibility of backtracking of
removed approximate instances. In this paper, we address the aforementioned issue
by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based
search algorithm, in the context of automated synthesis of approximate accelerators.
This enables the synthesis frameworks to deeply subsamples the design space of
approximate accelerator synthesis toward most promising approximate instances
based on the required performance goals, i.e., power consumption, area, or/and
delay. We investigated the challenges of providing an efficient open-source framework
that benefits analytical and search-based approximation techniques simultaneously
to both speed up the synthesis runtime and improve the quality of obtained results.
Besides, we studied the utilization of machine learning algorithms to improve
the performance of several critical steps, i.e., accelerator quality testing,
in the synthesis framework. The proposed framework can help the community to rapidly
generate efficient approximate accelerators in a reasonable runtime.
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
citation:
ama: 'Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators.
In: Proceedings of IEEE Computer Society Annual Symposium on VLSI. IEEE;
2021:384-389.'
apa: Awais, M., & Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient
Approximate Accelerators. Proceedings of IEEE Computer Society Annual Symposium
on VLSI, 384–389.
bibtex: '@inproceedings{Awais_Platzner_2021, title={MCTS-Based Synthesis Towards
Efficient Approximate Accelerators}, booktitle={Proceedings of IEEE Computer Society
Annual Symposium on VLSI}, publisher={IEEE}, author={Awais, Muhammad and Platzner,
Marco}, year={2021}, pages={384–389} }'
chicago: Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient
Approximate Accelerators.” In Proceedings of IEEE Computer Society Annual Symposium
on VLSI, 384–89. IEEE, 2021.
ieee: M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate
Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on
VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
mla: Awais, Muhammad, and Marco Platzner. “MCTS-Based Synthesis Towards Efficient
Approximate Accelerators.” Proceedings of IEEE Computer Society Annual Symposium
on VLSI, IEEE, 2021, pp. 384–89.
short: 'M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium
on VLSI, IEEE, 2021, pp. 384–389.'
conference:
end_date: 2021-07-09
location: Tampa, Florida USA (Virtual)
name: IEEE Computer Society Annual Symposium on VLSI
start_date: 2021-07-07
date_created: 2021-06-14T14:05:17Z
date_updated: 2022-01-06T06:55:31Z
department:
- _id: '78'
keyword:
- Approximate computing
- Design space exploration
- Accelerator synthesis
language:
- iso: eng
page: 384-389
publication: Proceedings of IEEE Computer Society Annual Symposium on VLSI
publisher: IEEE
status: public
title: MCTS-Based Synthesis Towards Efficient Approximate Accelerators
type: conference
user_id: '64665'
year: '2021'
...
---
_id: '16853'
abstract:
- lang: eng
text: State-of-the-art frameworks for generating approximate circuits usually rely
on information gained through circuit synthesis and/or verification to explore
the search space and to find an optimal solution. Throughout the process, a large
number of circuits may be subject to processing, leading to considerable runtimes.
In this work, we propose a search which takes error bounds and pre-computed impact
factors into account to reduce the number of invoked synthesis and verification
processes. In our experimental results, we achieved speed-ups of up to 76x while
area savings remain comparable to the reference search method, simulated annealing.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop
on Approximate Computing (AxC 2019).'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Fourth Workshop on Approximate Computing (AxC 2019).'
bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop
on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh
Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth
Workshop on Approximate Computing (AxC 2019). .'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).'
short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth
Workshop on Approximate Computing (AxC 2019) (n.d.).
date_created: 2020-04-25T08:02:07Z
date_updated: 2022-01-06T06:52:57Z
ddc:
- '006'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-04-25T08:00:35Z
date_updated: 2020-04-25T08:00:35Z
file_id: '16854'
file_name: AxC19_paper_3.pdf
file_size: 152806
relation: main_file
success: 1
file_date_updated: 2020-04-25T08:00:35Z
has_accepted_license: '1'
keyword:
- Approximate computing
- parameter selection
- search space exploration
- verification
- circuit synthesis
language:
- iso: eng
page: '2'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Fourth Workshop on Approximate Computing (AxC 2019)
publication_status: accepted
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: preprint
user_id: '49051'
year: '2019'
...
---
_id: '2200'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework
for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int.
Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance
Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.
Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY,
USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures}, DOI={10.1145/1950413.1950448},
booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM},
author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke,
Michael}, year={2011}, pages={177–180} }'
chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA),
177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.'
ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc.
Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:
10.1145/1950413.1950448.'
mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration
of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate
Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on
Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.'
date_created: 2018-04-03T15:08:13Z
date_updated: 2023-09-26T13:45:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/1950413.1950448
keyword:
- design space exploration
- LLVM
- partitioning
- performance
- estimation
- funding-intel
language:
- iso: eng
page: 177-180
place: New York, NY, USA
publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)
publication_identifier:
isbn:
- 978-1-4503-0554-9
publisher: ACM
quality_controlled: '1'
status: public
title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '37007'
abstract:
- lang: eng
text: UML is widely applied for the specification and modeling of software and some
studies have demonstrated that it is applicable for HW/SW codesign. However, in
this area there is still a big gap from UML modeling to SystemC-based verification
and synthesis environments. This paper presents an efficient approach to bridge
this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework
for the seamless integration of a customized SysML entry with code generation
for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the
SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate
the applicability of our approach.
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Da
full_name: He, Da
last_name: He
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and
Simulation of Combined HW/SW Systems. In: Proceedings of DATE’10. IEEE;
2010. doi:10.1109/DATE.2010.5456990'
apa: Mischkalla, F., He, D., & Müller, W. (2010). Closing the Gap between UML-based
Modeling and Simulation of Combined HW/SW Systems. Proceedings of DATE’10.
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE
2010), Dresden. https://doi.org/10.1109/DATE.2010.5456990
bibtex: '@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing
the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems},
DOI={10.1109/DATE.2010.5456990},
booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian
and He, Da and Müller, Wolfgang}, year={2010} }'
chicago: 'Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between
UML-Based Modeling and Simulation of Combined HW/SW Systems.” In Proceedings
of DATE’10. Dresden: IEEE, 2010. https://doi.org/10.1109/DATE.2010.5456990.'
ieee: 'F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling
and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation
& Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi:
10.1109/DATE.2010.5456990.'
mla: Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and
Simulation of Combined HW/SW Systems.” Proceedings of DATE’10, IEEE, 2010,
doi:10.1109/DATE.2010.5456990.
short: 'F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden,
2010.'
conference:
location: Dresden
name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:12:35Z
date_updated: 2023-01-17T09:12:44Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456990
keyword:
- Unified modeling language
- Field programmable gate arrays
- Bridges
- Helium
- Real time systems
- Operating systems
- Documentation
- Application software
- XML
- Space exploration
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
eisbn:
- 978-3-9810801-6-2
publisher: IEEE
status: public
title: Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW
Systems
type: conference
user_id: '5786'
year: '2010'
...