@inproceedings{36919,
  abstract     = {{Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a "loosely-timed" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability.}},
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  keywords     = {{Time-varying systems, Time-domain analysis, Synchronization, Context modeling, Clocks, Semantics, Standards}},
  publisher    = {{IEEE}},
  title        = {{{Efficient Power-Intent Validation Using "Loosely-Timed" Simulation Models: A Non-Invasive Approach}}},
  doi          = {{10.1109/PATMOS.2013.6662171}},
  year         = {{2013}},
}