@article{29049, abstract = {{This study investigates the conditions under which tax rate changes accelerate risky investments. While tax rate increases are often expected to harm investment, analytical studies find tax rate increases may foster investment under flexibility.We design a theorybased experimentwith a binomial random walk and entry–exit flexibility.We find accelerated investment upon tax rate increases irrespective of an exit option, but no corresponding response to tax cuts. This asymmetry may be due to tax salience and mechanisms from irreversible choice under uncertainty. Given this evidence of unexpected tax-reform effects, tax policymakers should carefully consider behavioral aspects.}}, author = {{Fahr, René and Janssen, Elmar A. and Sureth-Sloane, Caren}}, journal = {{FinanzArchiv / European Journal of Public Finance}}, keywords = {{Economic ExperimentM, Investment Decisions, Tax Effects, Timing Flexibility, Uncertainty}}, number = {{1-2}}, pages = {{239--289}}, title = {{{Can Tax Rate Changes Accelerate Investment under Entry and Exit Flexibility? – Insights from an Economic Experiment}}}, volume = {{78}}, year = {{2022}}, } @inproceedings{17667, abstract = {{Resolving distributed attacks benefits from collaboration between networks. We present three approaches for the same multi-domain defensive action that can be applied in such an alliance: 1) Counteract Everywhere, 2) Minimize Countermeasures, and 3) Minimize Propagation. First, we provide a formula to compute efficiency of a defense; then we use this formula to compute the efficiency of the approaches under various circumstances. Finally, we discuss how task execution order and timing influence defense efficiency. Our results show that the Minimize Propagation approach is the most efficient method when defending against the chosen attack.}}, author = {{Koning, Ralph and Polevoy, Gleb and Meijer, Lydia and de Laat, Cees and Grosso, Paola}}, booktitle = {{2019 6th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud)/ 2019 5th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom)}}, issn = {{null}}, keywords = {{computer network security, multinetwork environments, multidomain defensive action, task execution order, timing influence defense efficiency, distributed attacks, collaborative security defence approach, minimize propagation approach, minimize countermeasure approach, counteract everywhere approach, Conferences, Cloud computing, Computer crime, Edge computing, Security, Defense Approaches, Multi-Domain Defense, Collaborative Defense, Defense Algorithms, Computer Networks}}, pages = {{113--123}}, title = {{{Approaches for Collaborative Security Defences in Multi Network Environments}}}, doi = {{10.1109/CSCloud/EdgeCom.2019.000-9}}, year = {{2019}}, } @inproceedings{37009, abstract = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}}, author = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Assertion-Based Verification of RTOS Properties}}}, doi = {{10.1109/DATE.2010.5457130}}, year = {{2010}}, } @inproceedings{37011, abstract = {{Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study.}}, author = {{Klobedanz, Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10, Dresden}}, keywords = {{Timing, Programming, Automotive engineering, Application software, Hardware, Computer architecture, Communication system software, Software architecture, Delay, Software standards}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study}}}, doi = {{10.1109/DATE.2010.5457125}}, year = {{2010}}, } @inproceedings{37040, abstract = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}}, author = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}}, doi = {{10.1109/DATE.2010.5456965}}, year = {{2010}}, } @inproceedings{37053, abstract = {{Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.}}, author = {{Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}}, booktitle = {{Proceedings of HLDVT2010}}, keywords = {{Hardware, Microprogramming, Application software, Timing, Protocols, Virtual prototyping, Real time systems, Sampling methods, Operating systems, Emulation}}, location = {{Anaheim, FL, USA}}, publisher = {{IEEE}}, title = {{{Verification of Real-Time Properties for Hardware-Dependant Software}}}, year = {{2010}}, } @inproceedings{37039, abstract = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}}, author = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}}, doi = {{10.1109/DATE.2010.5456965}}, year = {{2010}}, } @inproceedings{37066, abstract = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.}}, author = {{Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE'09}}, isbn = {{978-1-4244-3781-8}}, keywords = {{Timing, Analytical models, Clocks, Performance analysis, Scheduling, Operating systems, Delay, Real time systems, Application software, Context modeling}}, title = {{{Increased Accuracy through Noise Injection in Abstract RTOS Simulation}}}, doi = {{10.1109/DATE.2009.5090925}}, year = {{2009}}, } @inproceedings{39502, abstract = {{The authors present a new approach to an interactive design and analysis environment for visual languages. The main components, i.e., editor animator and interpreter are introduced. Their interactions are being investigated emphasizing the interpreter-animator interaction and defining an interface supporting different levels of automation. The interpreter performs the executions on a logical level and triggers the animator. The interactive animation provides a very high degree of liveness since it is based on the tight integration of the animator and editor. The proposed architecture permits the distributed implementation of a system for real-time animation. Their concepts are validated by the implementation of a debugging environment for the complete visual programming language Pictorial Janus.}}, author = {{Dücker, M. and Lehrenfeld, Georg and Müller, Wolfgang and Tahedl, C.}}, booktitle = {{ Proceedings International Conference and Workshop on Engineering of Computer-Based Systems}}, isbn = {{0-8186-7889-5}}, keywords = {{Real time systems, Animation, Debugging, Automation, Computer languages, Timing, Environmental management, Programming environments, Visualization, Multimedia systems}}, location = {{Monterey, CA, USA }}, title = {{{A Generic System for Interactive Real--Time Animation}}}, doi = {{10.1109/ECBS.1997.581876}}, year = {{1997}}, } @inproceedings{39541, abstract = {{We investigate a translation of SDL diagrams into the complete visual representation of Pictorial Janus (PJ) programs in order to analyze the specification by visual debugging and animation. We additionally introduce timing concepts to PJ (Timed PJ) for a mapping of the SDL timing statements. The concepts transforming SDL interaction and process diagrams into Timed PJ are outlined by an example sketching the transformation of an Ethernet CSMA/CD protocol specification.}}, author = {{Lehrenfeld, Georg and Müller, Wolfgang and Tahedl, C.}}, booktitle = {{Proceedings of Symposium on Visual Languages}}, isbn = {{0-8186-7045-2}}, keywords = {{Animation, Timing, Debugging, Ethernet networks, Multiaccess communication, Protocols, Computer languages, Prototypes, Environmental management, Visualization}}, title = {{{Transforming SDL Diagrams Into a Complete Visual Representation}}}, doi = {{10.1109/VL.1995.520803}}, year = {{1995}}, } @inproceedings{39538, abstract = {{This article discusses the application of Pictorial Janus (PJ) for the rapid development and analysis of protocols by animation and complete visualization. In order to make PJ applicable in the context of hardware description we first extend PJ by timing facilities (Timed PJ) and introduce an approach for integrating VHDL models into this visual framework preserving the simulation semantics of VHDL. We finally give the example of the specification and animation of a non interlocked protocol.}}, author = {{Müller, Wolfgang and Lehrenfeld, Georg and Tahedl, C.}}, booktitle = {{Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair}}, isbn = {{4-930813-67-0}}, keywords = {{Animation, Protocols, Timing, Computer languages, Electronic mail, Context modeling, Visualization, Control systems, Flow graphs, Trademarks}}, title = {{{Complete Visual Specification and Animations of Protocols}}}, doi = {{10.1109/ASPDAC.1995.486383}}, year = {{1995}}, }