@inproceedings{37048,
  abstract     = {{We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.}},
  author       = {{Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}},
  editor       = {{Kleinjohann, L. and Kleinjohann, B.}},
  isbn         = {{978-3-642-15233-7}},
  keywords     = {{Natural Language     UML     SystemVerilog     Testbenches}},
  publisher    = {{Springer Verlag}},
  title        = {{{Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}}},
  doi          = {{10.1007/978-3-642-15234-4_9}},
  year         = {{2010}},
}

@inproceedings{37047,
  abstract     = {{We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.}},
  author       = {{Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}},
  editor       = {{Kleinjohann, L. and Kleinjohann, B.}},
  isbn         = {{978-3-642-15233-7}},
  keywords     = {{Natural Language     UML     SystemVerilog     Testbenches}},
  publisher    = {{Springer Verlag}},
  title        = {{{Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}}},
  doi          = {{10.1007/978-3-642-15234-4_9}},
  year         = {{2010}},
}

@article{34563,
  abstract     = {{UML has been widely accepted by the software community for several years. As electronic systems design can no longer be seen as an isolated hardware design activity, UML becomes of significant interest as a unification language for systems description combining both HW and SW components. This article provides a comprehensive view of the UML applied to System-on-Chip (SoC) and hardware-related embedded systems design. The modeling concepts in the UML language are first introduced, including major diagrams for the representation of the behavior and the structure of systems. The principles behind application specific UML customizations (UML profiles) are summarized, and several examples relevant for SoC design are given, such as the SysML (System Modeling Language) and the SoC Profile. Thereafter, various approaches associating UML with existing HW/SW design languages are presented. Beyond language aspects, the article addresses the question of UML-based design flows, and shows how UML can be applied concretely to the development of electronic-based systems. The current situation about tool support constitutes the last focus of the article. In particular, we show how UML tools can be combined with well-known simulation environments, such as MATLAB.}},
  author       = {{Vanderperren, Yves and Müller, Wolfgang and Dahaene, Wim}},
  journal      = {{Design Automation for Embedded Systems}},
  keywords     = {{UML     SysML     Model-based design     System specification     Modelling languages}},
  pages        = {{261--292}},
  publisher    = {{Springer-Verlag}},
  title        = {{{UML for Electronic Systems Design – A Comprehensive Overview}}},
  doi          = {{10.1007/s10617-008-9028-9}},
  volume       = {{12}},
  year         = {{2008}},
}

@inproceedings{39030,
  abstract     = {{StateCharts are well accepted for embedded systems
specification for various applications. However, for the
specification of complex systems they have several
limitations. In this article, we present a novel approach to
efficiently execute an UML 2.0 subset for embedded real-
time systems implementation with focus on hardware
interrupts, software exceptions, and timeouts. We
introduce a UML Virtual Machine, which directly
executes sequence diagrams, which are embedded into
hierarchically structured state transition diagrams.
Whereas state diagrams are directly executed as
Embedded State Machines (ESMs), sequence diagrams
are translated into UVM Bytecode. The final UVM
execution is performed by the interaction of the ESM and
the Bytecode Interpreter. Due to our completely model-
based approach, the UVM runtime kernel is easily
adaptable and scalable to different scheduling and
memory management strategies.}},
  author       = {{Schattkowsky, Tim and Müller, Wolfgang}},
  booktitle    = {{Proceedings of ISNG 05}},
  keywords     = {{UML, Executable Models, Hardware/Software Co-design, Virtual Machine, Embedded Systems}},
  title        = {{{A UML Virtual Machine for Embedded Systems}}},
  year         = {{2005}},
}

@article{34565,
  abstract     = {{The textual Object Constraint Language (OCL) is primarily intended to specify restrictions over UML class diagrams, in particular class invariants, operation pre-, and postconditions. Based on several improvements in the definition of the language concepts in last years, a proposal for a new version of OCL has recently been published [43]. That document provides an extensive OCL semantic description that constitutes a tight integration into UML. However, OCL still lacks a semantic integration of UML Statecharts, although it can already be used to refer to states in OCL expressions.

This article presents an approach that closes this gap and introduces a formal semantics for such integration through a mathematical model. It also presents the definition of a temporal OCL extension by means of a UML Profile based on the metamodel of the latest OCL proposal. Our OCL extension enables modelers to specify behavioral state-oriented real-time constraints. It provides an intuitive understanding and readability at application level since common OCL syntax and concepts are preserved. A well-defined formal semantics is given through the mapping of temporal OCL expressions to temporal logics formulae. }},
  author       = {{Flake, Stephan and Müller, Wolfgang}},
  journal      = {{Journal on Software and System Modeling (SoSyM)}},
  keywords     = {{Object Constraint Language     UML Statecharts     UML Profile     Real-time constraints     Temporal logics}},
  number       = {{3}},
  pages        = {{164--186}},
  publisher    = {{Springer-Verlag}},
  title        = {{{Formal Semantics of Static and Temporal State-Oriented OCL Constraints}}},
  doi          = {{10.1007/s10270-003-0026-x}},
  volume       = {{2}},
  year         = {{2003}},
}

@inproceedings{39364,
  abstract     = {{The textual Object Constraint Language (OCL) is an of-
ficial part of the Unified Modeling Language (UML). OCL
is primarily used to formulate restrictions over UML mod-
els, in particular, invariants and operation pre- and post-
conditions in the context of class diagrams. However, OCL
is missing means to specify constraints over the dynamic
behavior of a UML model. We have therefore developed a
temporal extension of OCL that enables modelers to specify
behavioral state-oriented constraints. That work provides
an alternative to the rather cryptic temporal logic formulae
that are commonly used to specify behavioral system prop-
erties.
This article now illustrates that our OCL extension al-
lows for specifying all kinds of properties that are regarded
as relevant in practice. We present according temporal OCL
expressions for property specification patterns that have
been identified in the area of formal specification.}},
  author       = {{Flake, Stephan and Müller, Wolfgang}},
  booktitle    = {{Proceedings of SERP'03}},
  keywords     = {{UML, Object Constraint Language, Patterns, Property Specification}},
  title        = {{{Expressing Property Specification Patterns with OCL}}},
  year         = {{2003}},
}

