@inproceedings{97,
  abstract     = {{Bridging the gap between informal, imprecise, and vague user requirements descriptions and precise formalized specifications is the main task of requirements engineering. Techniques such as interviews or story telling are used when requirements engineers try to identify a user's needs. The requirements specification process is typically done in a dialogue between users, domain experts, and requirements engineers. In our research, we aim at automating the specification of requirements. The idea is to distinguish between untrained users and trained users, and to exploit domain knowledge learned from previous runs of our system. We let untrained users provide unstructured natural language descriptions, while we allow trained users to provide examples of behavioral descriptions. In both cases, our goal is to synthesize formal requirements models similar to statecharts. From requirements specification processes with trained users, behavioral ontologies are learned which are later used to support the requirements specification process for untrained users. Our research method is original in combining natural language processing and search-based techniques for the synthesis of requirements specifications. Our work is embedded in a larger project that aims at automating the whole software development and deployment process in envisioned future software service markets.}},
  author       = {{van Rooijen, Lorijn and Bäumer, Frederik Simon and Platenius, Marie Christin and Geierhos, Michaela and Hamann, Heiko and Engels, Gregor}},
  booktitle    = {{2017 IEEE 25th International Requirements Engineering Conference Workshops (REW)}},
  isbn         = {{978-1-5386-3489-9}},
  keywords     = {{Software, Unified modeling language, Requirements engineering, Ontologies, Search problems, Natural languages}},
  location     = {{Lisbon, Portugal}},
  pages        = {{379--385}},
  publisher    = {{IEEE}},
  title        = {{{From User Demand to Software Service: Using Machine Learning to Automate the Requirements Specification Process}}},
  doi          = {{10.1109/REW.2017.26}},
  year         = {{2017}},
}

@inproceedings{37007,
  abstract     = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}},
  author       = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}},
  doi          = {{10.1109/DATE.2010.5456990}},
  year         = {{2010}},
}

@inproceedings{37067,
  abstract     = {{IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these descriptions at the XML level can be time-consuming and error-prone. In this paper, we show that the UML can be consistently applied as an efficient and comprehensible frontend for IP-XACT-based IP description and integration. For this, we present an IP-XACT UML profile that enables UML-based descriptions covering the same information as a corresponding IP-XACT description. This enables the automated generation of IP-XACT component and design descriptions from respective UML models. In particular, it also allows the integration of existing IPs with UML. To illustrate our approach, we present an application example based on the IBM PowerPC Evaluation Kit.}},
  author       = {{Schattkowsky, Tim and Xie, Tao and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE'09}},
  isbn         = {{978-1-4244-3781-8}},
  keywords     = {{Unified modeling language, XML, Power system modeling, Application software, Master-slave, Power system management, Acceleration, Scattering, Software engineering, Software standards}},
  publisher    = {{IEEE}},
  title        = {{{A UML Frontend for IP-XACT-based IP Management}}},
  doi          = {{10.1109/DATE.2009.5090664}},
  year         = {{2009}},
}

@inproceedings{39029,
  abstract     = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}},
  author       = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}},
  booktitle    = {{Proceedings of DATE’05}},
  isbn         = {{0-7695-2288-2}},
  keywords     = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}},
  publisher    = {{IEEE}},
  title        = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}},
  doi          = {{10.1109/DATE.2005.20}},
  year         = {{2005}},
}

@inproceedings{39032,
  abstract     = {{Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.}},
  author       = {{Schattkowsky, Tim and Müller, Wolfgang}},
  booktitle    = {{Proceedings of VL/HCC 05}},
  isbn         = {{0-7695-2443-5}},
  keywords     = {{Unified modeling language, Software design, Virtual machining, Embedded system, Programming, Documentation, Hardware, Computer languages, Operating systems, Runtime}},
  title        = {{{Transformation of UML State Machines for Direct Execution}}},
  doi          = {{10.1109/VLHCC.2005.64}},
  year         = {{2005}},
}

@inproceedings{39061,
  abstract     = {{This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML state diagrams, which are translated to the formal B language and are model checked for real-time properties. By means of the B language and a B theorem prover, refined state diagrams are verified against their abstract representation. The approach is presented by means of the refinement of a digital echo cancellation unit.}},
  author       = {{Krupp, Alexander and Müller, Wolfgang and Oliver, Ian}},
  booktitle    = {{Proceedings of DATE’04 Designers' Forum}},
  isbn         = {{0-7695-2085-5}},
  keywords     = {{Echo cancellers, Logic, Unified modeling language, Automata, Data structures, Boolean functions, Electronic design automation and methodology, Prototypes, Specification languages, Constraint theory}},
  title        = {{{Formal Refinement and Model Checking of An Echo Cancellation Unit}}},
  doi          = {{10.1109/DATE.2004.1269214}},
  year         = {{2004}},
}

@inproceedings{39069,
  abstract     = {{We present the syntax and semantics of a past- and future-oriented temporal extension of the Object Constraint Language (OCL). Our extension supports designers to express time-bounded properties over a state-oriented UML model of a system under development. The semantics is formally defined over the system states of a mathematical object model. Additionally, we present a mapping to Clocked Linear Temporal Logic (Clocked LTL) formulae, which is the basis for further application in verification with model checking. We demonstrate the applicability of the approach by the example of a buffer specification in the context of a production system.}},
  author       = {{Flake, Stephan and Müller, Wolfgang}},
  booktitle    = {{Proceedings of SEFM´04}},
  isbn         = {{0-7695-2222-X}},
  keywords     = {{Unified modeling language, Logic, Clocks, Boolean functions, Application software, Time factors, Real time systems, Formal verification, Buffer storage, Software packages}},
  publisher    = {{IEEE}},
  title        = {{{Past- and Future-Oriented Time-Bound Temporal Properties with OCL}}},
  doi          = {{10.1109/SEFM.2004.1347516}},
  year         = {{2004}},
}

@inproceedings{39403,
  abstract     = {{The Unified Modeling Language (UML) has received wide acceptance as a standard language in the field of software specification by means of different diagram types. In a recent version of UML, the textual Object Constraint Language (OCL) was introduced to support specification of constraints for UML models. But OCL currently does not provide sufficient means to specify constraints over the dynamic behavior of a model. This article presents an OCL extension that is consistent with current OCL and enables modelers to specify state-related time-bounded constraints. We consider the case study of a flexible manufacturing system and identify typical real-time constraints. The constraints are presented in our temporal OCL extension as well as in temporal logic formulae. For general application, we define a semantics of our OCL extension by means of a time-bounded temporal logic based on Computational Tree Logic (CTL).}},
  author       = {{Flake, Stephan and Müller, Wolfgang}},
  booktitle    = {{Proceedings of HICSS-35}},
  isbn         = {{0-7695-1435-9}},
  keywords     = {{Unified modeling language, Logic, Formal verification, Real time systems, Programming profession, Vehicle dynamics, Software standards, Flexible manufacturing systems, Electronics industry, Protocols}},
  location     = {{Big Island, HI, USA }},
  title        = {{{Specification of Real-Time Properties for UML Models}}},
  doi          = {{10.1109/HICSS.2002.994469}},
  year         = {{2002}},
}